From patchwork Tue Dec 27 15:21:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 89098 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp5036246qgi; Tue, 27 Dec 2016 07:28:26 -0800 (PST) X-Received: by 10.200.45.211 with SMTP id q19mr20417453qta.115.1482852506270; Tue, 27 Dec 2016 07:28:26 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id l126si18310403qkd.76.2016.12.27.07.28.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 27 Dec 2016 07:28:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cLtfr-0006j0-MN for patch@linaro.org; Tue, 27 Dec 2016 10:28:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35349) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cLtZg-00020j-OF for qemu-devel@nongnu.org; Tue, 27 Dec 2016 10:22:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cLtZf-0001EV-T7 for qemu-devel@nongnu.org; Tue, 27 Dec 2016 10:22:00 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47869) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cLtZf-0001EG-MW for qemu-devel@nongnu.org; Tue, 27 Dec 2016 10:21:59 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cLtZe-0003sz-Rf for qemu-devel@nongnu.org; Tue, 27 Dec 2016 15:21:58 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 27 Dec 2016 15:21:01 +0000 Message-Id: <1482852077-19397-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1482852077-19397-1-git-send-email-peter.maydell@linaro.org> References: <1482852077-19397-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/25] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The GICv3 requires that we only signal Pending interrupts to the CPU. This category does not include Pending+Active interrupts, which means we need to check whether the interrupt is Active in the gicr_int_pending() and gicd_int_pending() functions. Interrupts are rarely in the Active+Pending state, but KVM uses this as part of its handling of the virtual timer, so this bug was causing KVM to go into an infinite loop of taking the vtimer interrupt when the guest first triggered it. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- hw/intc/arm_gicv3.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 8a6c647..f0c967b 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -54,6 +54,7 @@ static uint32_t gicd_int_pending(GICv3State *s, int irq) * + the PENDING latch is set OR it is level triggered and the input is 1 * + its ENABLE bit is set * + the GICD enable bit for its group is set + * + its ACTIVE bit is not set (otherwise it would be Active+Pending) * Conveniently we can bulk-calculate this with bitwise operations. */ uint32_t pend, grpmask; @@ -63,9 +64,11 @@ static uint32_t gicd_int_pending(GICv3State *s, int irq) uint32_t group = *gic_bmp_ptr32(s->group, irq); uint32_t grpmod = *gic_bmp_ptr32(s->grpmod, irq); uint32_t enable = *gic_bmp_ptr32(s->enabled, irq); + uint32_t active = *gic_bmp_ptr32(s->active, irq); pend = pending | (~edge_trigger & level); pend &= enable; + pend &= ~active; if (s->gicd_ctlr & GICD_CTLR_DS) { grpmod = 0; @@ -96,12 +99,14 @@ static uint32_t gicr_int_pending(GICv3CPUState *cs) * + the PENDING latch is set OR it is level triggered and the input is 1 * + its ENABLE bit is set * + the GICD enable bit for its group is set + * + its ACTIVE bit is not set (otherwise it would be Active+Pending) * Conveniently we can bulk-calculate this with bitwise operations. */ uint32_t pend, grpmask, grpmod; pend = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level); pend &= cs->gicr_ienabler0; + pend &= ~cs->gicr_iactiver0; if (cs->gic->gicd_ctlr & GICD_CTLR_DS) { grpmod = 0;