From patchwork Thu Jan 19 14:09:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 91921 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp297944qgi; Thu, 19 Jan 2017 06:18:18 -0800 (PST) X-Received: by 10.200.56.4 with SMTP id q4mr8387377qtb.73.1484835498212; Thu, 19 Jan 2017 06:18:18 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s63si2681537qkc.208.2017.01.19.06.18.17 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 19 Jan 2017 06:18:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48572 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cUDXb-0006lC-DT for patch@linaro.org; Thu, 19 Jan 2017 09:18:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47444) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cUDPq-0000xs-M9 for qemu-devel@nongnu.org; Thu, 19 Jan 2017 09:10:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cUDPo-00059a-Lh for qemu-devel@nongnu.org; Thu, 19 Jan 2017 09:10:14 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48208) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cUDPo-00055o-E9 for qemu-devel@nongnu.org; Thu, 19 Jan 2017 09:10:12 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cUDPi-0003Bl-Nz for qemu-devel@nongnu.org; Thu, 19 Jan 2017 14:10:06 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 19 Jan 2017 14:09:42 +0000 Message-Id: <1484834995-26826-24-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484834995-26826-1-git-send-email-peter.maydell@linaro.org> References: <1484834995-26826-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 23/36] target-arm: Add ARMCPU fields for GIC CPU i/f config X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add fields to the ARMCPU structure to allow CPU classes to specify the configurable aspects of their GIC CPU interface. In particular, the virtualization support allows different values for number of list registers, priority bits and preemption bits. Signed-off-by: Peter Maydell Acked-by: Alistair Francis Message-id: 1483977924-14522-6-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 6 ++++++ 2 files changed, 11 insertions(+) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fa09498..16c7c10 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -662,6 +662,11 @@ struct ARMCPU { uint32_t dcz_blocksize; uint64_t rvbar; + /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ + int gic_num_lrs; /* number of list registers */ + int gic_vpribits; /* number of virtual priority bits */ + int gic_vprebits; /* number of virtual preemption bits */ + ARMELChangeHook *el_change_hook; void *el_change_hook_opaque; }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 549cb1e..73c7f31 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -147,6 +147,9 @@ static void aarch64_a57_initfn(Object *obj) cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } @@ -201,6 +204,9 @@ static void aarch64_a53_initfn(Object *obj) cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); }