From patchwork Fri Jan 27 15:32:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 92689 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp297010qgi; Fri, 27 Jan 2017 07:51:46 -0800 (PST) X-Received: by 10.55.97.207 with SMTP id v198mr9322864qkb.242.1485532305973; Fri, 27 Jan 2017 07:51:45 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id w64si3779046qte.260.2017.01.27.07.51.45 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 27 Jan 2017 07:51:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46364 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX8oR-000497-IT for patch@linaro.org; Fri, 27 Jan 2017 10:51:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59690) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX8Vu-00016f-Qu for qemu-devel@nongnu.org; Fri, 27 Jan 2017 10:32:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cX8Vu-0005A3-5I for qemu-devel@nongnu.org; Fri, 27 Jan 2017 10:32:34 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48311) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cX8Vt-00055y-V8 for qemu-devel@nongnu.org; Fri, 27 Jan 2017 10:32:34 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cX8Vi-0003O7-PN for qemu-devel@nongnu.org; Fri, 27 Jan 2017 15:32:22 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 27 Jan 2017 15:32:04 +0000 Message-Id: <1485531137-2362-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1485531137-2362-1-git-send-email-peter.maydell@linaro.org> References: <1485531137-2362-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/22] target/arm: Drop IS_M() macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We only use the IS_M() macro in two places, and it's a bit of a namespace grab to put in cpu.h. Drop it in favour of just explicitly calling arm_feature() in the places where it was used. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 1485285380-10565-2-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 6 ------ target/arm/cpu.c | 2 +- target/arm/helper.c | 2 +- 3 files changed, 2 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 521c11b..b2cc329 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1762,12 +1762,6 @@ bool write_list_to_cpustate(ARMCPU *cpu); */ bool write_cpustate_to_list(ARMCPU *cpu); -/* Does the core conform to the "MicroController" profile. e.g. Cortex-M3. - Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are - conventional cores (ie. Application or Realtime profile). */ - -#define IS_M(env) arm_feature(env, ARM_FEATURE_M) - #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9075989..6395d5a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -182,7 +182,7 @@ static void arm_cpu_reset(CPUState *s) /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is * clear at reset. Initial SP and PC are loaded from ROM. */ - if (IS_M(env)) { + if (arm_feature(env, ARM_FEATURE_M)) { uint32_t initial_msp; /* Loaded from 0x0 */ uint32_t initial_pc; /* Loaded from 0x4 */ uint8_t *rom; diff --git a/target/arm/helper.c b/target/arm/helper.c index cfbc622..ce7e43b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6695,7 +6695,7 @@ void arm_cpu_do_interrupt(CPUState *cs) CPUARMState *env = &cpu->env; unsigned int new_el = env->exception.target_el; - assert(!IS_M(env)); + assert(!arm_feature(env, ARM_FEATURE_M)); arm_log_exception(cs->exception_index); qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),