diff mbox series

[PULL,14/22] armv7m: set CFSR.UNDEFINSTR on undefined instructions

Message ID 1485531137-2362-15-git-send-email-peter.maydell@linaro.org
State Accepted
Commit 81dd9648c69bb89afdd6f4bb3ed6f3efdac96524
Headers show
Series target-arm queue | expand

Commit Message

Peter Maydell Jan. 27, 2017, 3:32 p.m. UTC 
From: Michael Davidsaver <mdavidsaver@gmail.com>


When we take an exception for an undefined instruction, set the
appropriate CFSR bit.

Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 1485285380-10565-7-git-send-email-peter.maydell@linaro.org
[PMM: tweaked commit message, comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper.c | 1 +
 1 file changed, 1 insertion(+)

-- 
2.7.4
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7dc30f5..e6b1c36 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6072,6 +6072,7 @@  void arm_v7m_cpu_do_interrupt(CPUState *cs)
     switch (cs->exception_index) {
     case EXCP_UDEF:
         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+        env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK;
         return;
     case EXCP_SWI:
         /* The PC already points to the next instruction.  */