diff mbox series

[2/9] armv7m: Implement reading and writing of PRIGROUP

Message ID 1486065742-28639-3-git-send-email-peter.maydell@linaro.org
State Superseded
Headers show
Series Rewrite NVIC to not depend on the GIC | expand

Commit Message

Peter Maydell Feb. 2, 2017, 8:02 p.m. UTC
Add a state field for the v7M PRIGROUP register and implent
reading and writing it. The current NVIC doesn't honour
the values written, but the new version will.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 hw/intc/armv7m_nvic.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

-- 
2.7.4

Comments

Philippe Mathieu-Daudé Feb. 10, 2017, 2:27 p.m. UTC | #1
On 02/02/2017 05:02 PM, Peter Maydell wrote:
> Add a state field for the v7M PRIGROUP register and implent

> reading and writing it. The current NVIC doesn't honour

> the values written, but the new version will.

>

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


> ---

>  hw/intc/armv7m_nvic.c | 14 ++++++++------

>  1 file changed, 8 insertions(+), 6 deletions(-)

>

> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

> index 09975f3..ce22001 100644

> --- a/hw/intc/armv7m_nvic.c

> +++ b/hw/intc/armv7m_nvic.c

> @@ -24,6 +24,9 @@

>  typedef struct NVICState {

>      GICState gic;

>      ARMCPU *cpu;

> +

> +    uint32_t prigroup;

> +

>      struct {

>          uint32_t control;

>          uint32_t reload;

> @@ -223,7 +226,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)

>      case 0xd08: /* Vector Table Offset.  */

>          return cpu->env.v7m.vecbase;

>      case 0xd0c: /* Application Interrupt/Reset Control.  */

> -        return 0xfa050000;

> +        return 0xfa050000 | (s->prigroup << 8);

>      case 0xd10: /* System Control.  */

>          /* TODO: Implement SLEEPONEXIT.  */

>          return 0;

> @@ -362,9 +365,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)

>              if (value & 1) {

>                  qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");

>              }

> -            if (value & 0x700) {

> -                qemu_log_mask(LOG_UNIMP, "PRIGROUP unimplemented\n");

> -            }

> +            s->prigroup = extract32(value, 8, 3);

>          }

>          break;

>      case 0xd10: /* System Control.  */

> @@ -483,13 +484,14 @@ static const MemoryRegionOps nvic_sysreg_ops = {

>

>  static const VMStateDescription vmstate_nvic = {

>      .name = "armv7m_nvic",

> -    .version_id = 1,

> -    .minimum_version_id = 1,

> +    .version_id = 2,

> +    .minimum_version_id = 2,

>      .fields = (VMStateField[]) {

>          VMSTATE_UINT32(systick.control, NVICState),

>          VMSTATE_UINT32(systick.reload, NVICState),

>          VMSTATE_INT64(systick.tick, NVICState),

>          VMSTATE_TIMER_PTR(systick.timer, NVICState),

> +        VMSTATE_UINT32(prigroup, NVICState),

>          VMSTATE_END_OF_LIST()

>      }

>  };

>
Alex Bennée Feb. 14, 2017, 5:08 p.m. UTC | #2
Peter Maydell <peter.maydell@linaro.org> writes:

> Add a state field for the v7M PRIGROUP register and implent

> reading and writing it. The current NVIC doesn't honour

> the values written, but the new version will.

>

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  hw/intc/armv7m_nvic.c | 14 ++++++++------

>  1 file changed, 8 insertions(+), 6 deletions(-)

>

> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

> index 09975f3..ce22001 100644

> --- a/hw/intc/armv7m_nvic.c

> +++ b/hw/intc/armv7m_nvic.c

> @@ -24,6 +24,9 @@

>  typedef struct NVICState {

>      GICState gic;

>      ARMCPU *cpu;

> +

> +    uint32_t prigroup;


It might be worth mentioning the field resets to 0b000 here.
Nevertheless:

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> +

>      struct {

>          uint32_t control;

>          uint32_t reload;

> @@ -223,7 +226,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)

>      case 0xd08: /* Vector Table Offset.  */

>          return cpu->env.v7m.vecbase;

>      case 0xd0c: /* Application Interrupt/Reset Control.  */

> -        return 0xfa050000;

> +        return 0xfa050000 | (s->prigroup << 8);

>      case 0xd10: /* System Control.  */

>          /* TODO: Implement SLEEPONEXIT.  */

>          return 0;

> @@ -362,9 +365,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)

>              if (value & 1) {

>                  qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");

>              }

> -            if (value & 0x700) {

> -                qemu_log_mask(LOG_UNIMP, "PRIGROUP unimplemented\n");

> -            }

> +            s->prigroup = extract32(value, 8, 3);

>          }

>          break;

>      case 0xd10: /* System Control.  */

> @@ -483,13 +484,14 @@ static const MemoryRegionOps nvic_sysreg_ops = {

>

>  static const VMStateDescription vmstate_nvic = {

>      .name = "armv7m_nvic",

> -    .version_id = 1,

> -    .minimum_version_id = 1,

> +    .version_id = 2,

> +    .minimum_version_id = 2,

>      .fields = (VMStateField[]) {

>          VMSTATE_UINT32(systick.control, NVICState),

>          VMSTATE_UINT32(systick.reload, NVICState),

>          VMSTATE_INT64(systick.tick, NVICState),

>          VMSTATE_TIMER_PTR(systick.timer, NVICState),

> +        VMSTATE_UINT32(prigroup, NVICState),

>          VMSTATE_END_OF_LIST()

>      }

>  };



--
Alex Bennée
diff mbox series

Patch

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 09975f3..ce22001 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -24,6 +24,9 @@ 
 typedef struct NVICState {
     GICState gic;
     ARMCPU *cpu;
+
+    uint32_t prigroup;
+
     struct {
         uint32_t control;
         uint32_t reload;
@@ -223,7 +226,7 @@  static uint32_t nvic_readl(NVICState *s, uint32_t offset)
     case 0xd08: /* Vector Table Offset.  */
         return cpu->env.v7m.vecbase;
     case 0xd0c: /* Application Interrupt/Reset Control.  */
-        return 0xfa050000;
+        return 0xfa050000 | (s->prigroup << 8);
     case 0xd10: /* System Control.  */
         /* TODO: Implement SLEEPONEXIT.  */
         return 0;
@@ -362,9 +365,7 @@  static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
             if (value & 1) {
                 qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
             }
-            if (value & 0x700) {
-                qemu_log_mask(LOG_UNIMP, "PRIGROUP unimplemented\n");
-            }
+            s->prigroup = extract32(value, 8, 3);
         }
         break;
     case 0xd10: /* System Control.  */
@@ -483,13 +484,14 @@  static const MemoryRegionOps nvic_sysreg_ops = {
 
 static const VMStateDescription vmstate_nvic = {
     .name = "armv7m_nvic",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(systick.control, NVICState),
         VMSTATE_UINT32(systick.reload, NVICState),
         VMSTATE_INT64(systick.tick, NVICState),
         VMSTATE_TIMER_PTR(systick.timer, NVICState),
+        VMSTATE_UINT32(prigroup, NVICState),
         VMSTATE_END_OF_LIST()
     }
 };