From patchwork Mon Apr 24 16:33:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 98143 Delivered-To: patch@linaro.org Received: by 10.182.246.10 with SMTP id xs10csp340909obc; Mon, 24 Apr 2017 09:35:11 -0700 (PDT) X-Received: by 10.237.36.151 with SMTP id t23mr28103777qtc.181.1493051711588; Mon, 24 Apr 2017 09:35:11 -0700 (PDT) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id t184si18547253qkh.288.2017.04.24.09.35.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 24 Apr 2017 09:35:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45059 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2gxD-0006IA-3e for patch@linaro.org; Mon, 24 Apr 2017 12:35:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2gvx-0005Tu-32 for qemu-devel@nongnu.org; Mon, 24 Apr 2017 12:33:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2gvw-00036a-8t for qemu-devel@nongnu.org; Mon, 24 Apr 2017 12:33:53 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36910) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2gvq-00031J-RN; Mon, 24 Apr 2017 12:33:46 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1d2gvg-0002pF-RV; Mon, 24 Apr 2017 17:33:36 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 24 Apr 2017 17:33:33 +0100 Message-Id: <1493051615-30715-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493051615-30715-1-git-send-email-peter.maydell@linaro.org> References: <1493051615-30715-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [RFC 1/3] arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When identifying the DFSR format for an alignment fault, use the mmu index that we are passed, rather than calling cpu_mmu_index() to get the mmu index for the current CPU state. This doesn't actually make any difference since the only cases where the current MMU index differs from the index used for the load are the "unprivileged load/store" instructions, and in that case the mmu index may differ but the translation regime is the same (apart from the "use from Hyp mode" case which is UNPREDICTABLE). However it's the more logical thing to do. Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 156b825..de24815 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -208,7 +208,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format */ - if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { + if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { env->exception.fsr = (1 << 9) | 0x21; } else { env->exception.fsr = 0x1;