| Message ID | 1493122030-32191-7-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | armv7m: Implement MPU support | expand |
On Tue, Apr 25, 2017 at 5:07 AM, Peter Maydell <peter.maydell@linaro.org> wrote: > If the CPU is a PMSA config with no MPU implemented, then the > SCTLR.M bit should be RAZ/WI, so that the guest can never > turn on the non-existent MPU. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Thanks, Alistair > --- > target/arm/helper.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 404bfdb..f0f25c8 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3258,6 +3258,11 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, > return; > } > > + if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { > + /* M bit is RAZ/WI for PMSA with no MPU implemented */ > + value &= ~SCTLR_M; > + } > + > raw_write(env, ri, value); > /* ??? Lots of these bits are not implemented. */ > /* This may enable/disable the MMU, so do a TLB flush. */ > -- > 2.7.4 > >
On 05/03/2017 06:30 PM, Alistair Francis wrote: > On Tue, Apr 25, 2017 at 5:07 AM, Peter Maydell <peter.maydell@linaro.org> wrote: >> If the CPU is a PMSA config with no MPU implemented, then the >> SCTLR.M bit should be RAZ/WI, so that the guest can never >> turn on the non-existent MPU. >> >> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > > Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > > Thanks, > > Alistair > >> --- >> target/arm/helper.c | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 404bfdb..f0f25c8 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -3258,6 +3258,11 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, >> return; >> } >> >> + if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { >> + /* M bit is RAZ/WI for PMSA with no MPU implemented */ >> + value &= ~SCTLR_M; >> + } >> + >> raw_write(env, ri, value); >> /* ??? Lots of these bits are not implemented. */ >> /* This may enable/disable the MMU, so do a TLB flush. */ >> -- >> 2.7.4 >> >> >
diff --git a/target/arm/helper.c b/target/arm/helper.c index 404bfdb..f0f25c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3258,6 +3258,11 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } + if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { + /* M bit is RAZ/WI for PMSA with no MPU implemented */ + value &= ~SCTLR_M; + } + raw_write(env, ri, value); /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */
If the CPU is a PMSA config with no MPU implemented, then the SCTLR.M bit should be RAZ/WI, so that the guest can never turn on the non-existent MPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4