From patchwork Thu Jun 1 17:10:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100955 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp859226obc; Thu, 1 Jun 2017 10:16:16 -0700 (PDT) X-Received: by 10.237.53.205 with SMTP id d13mr2780248qte.46.1496337376633; Thu, 01 Jun 2017 10:16:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337376; cv=none; d=google.com; s=arc-20160816; b=DsH3HgCtTwg94lxle4/Lnh3mEVdp3+/PHhTvlNlfEyIPS0E2HSyKmT1B5FdNUT6Vc3 A7ziX/4HULSzqQWhZLGdB/l/Vimtur4+kA5tPdy38d8e9l7NMUCm0DEjcHsf79n8WvD6 o5vuyZ/ei8FxVgLhGEN6lj48j5lm2jAppkeGjwrzZROGsx7kvKT5Z6wuhVsbwwUDRpOR obweDe2F7Ot7c+/m40Lw30119t36zWDdIKNRFPa43AdaUKAR49GTDUetqHSGb1Lmrg4T WiJwzqY4m0auh6S2znYRC7UwscvnM7vaa4+uUEQKFHdaoItOFmBuIY3S8RLVoUO5kS7R DG1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=/a7FRICu6Pm7wcC+R+ZzbFcQzp/hMYtV5NZ8IeexTKw=; b=CQt6xP08mK0dv4pxgd4r620YT0k4w9lfckEhuGlZLmg/PQCzTyZuI7hlsY7S3D+sEY 1cG/1aqPjCMZAa1X7UnueE//cKZqQaRcWZIbZBn6lT3oWEDuM+AIPxF3qivxJ0WGPWJO ob0kOneVfey5H2vzVYP5HbFLJLMzvypPB9phwlSF6lc/CrLSqXLbJ+lcZEqPemttyfv1 Q30pgnyylRarCXqri2cp51yuK9EC542UQz9ETkWuMUKiYl1Tz25t1mSVejo63Uh/4qzt pZ4vDfoiWbbtNWzIJ6bWOraozpXxhpKNV/bMkqGBJwx8xcC/vxKCNT7MH3/Alnz97XCb NMCA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f95si19750410qtb.88.2017.06.01.10.16.16 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:16:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45823 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGThl-0005qc-Tl for patch@linaro.org; Thu, 01 Jun 2017 13:16:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35116) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcV-00014m-V9 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcU-00068v-P4 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcU-00064g-Gg for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:46 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcQ-0007Pb-7d for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:42 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:17 +0100 Message-Id: <1496337035-30213-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/27] arm: Use different ARMMMUIdx values for M profile X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make M profile use completely separate ARMMMUIdx values from those that A profile CPUs use. This is a prelude to adding support for the MPU and for v8M, which together will require 6 MMU indexes which don't map cleanly onto the A profile uses: non secure User non secure Privileged non secure Privileged, execution priority < 0 secure User secure Privileged secure Privileged, execution priority < 0 Signed-off-by: Peter Maydell Message-id: 1493122030-32191-4-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 21 +++++++++++++++++++-- target/arm/helper.c | 5 +++++ target/arm/translate.c | 3 +++ 3 files changed, 27 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4b1e982..cadec09 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2057,8 +2057,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * of the AT/ATS operations. * The values used are carefully arranged to make mmu_idx => EL lookup easy. */ -#define ARM_MMU_IDX_A 0x10 /* A profile (and M profile, for the moment) */ +#define ARM_MMU_IDX_A 0x10 /* A profile */ #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ +#define ARM_MMU_IDX_M 0x40 /* M profile */ #define ARM_MMU_IDX_TYPE_MASK (~0x7) #define ARM_MMU_IDX_COREIDX_MASK 0x7 @@ -2071,6 +2072,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, + ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, + ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ @@ -2089,6 +2092,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_S1SE0 = 1 << 4, ARMMMUIdxBit_S1SE1 = 1 << 5, ARMMMUIdxBit_S2NS = 1 << 6, + ARMMMUIdxBit_MUser = 1 << 0, + ARMMMUIdxBit_MPriv = 1 << 1, } ARMMMUIdxBit; #define MMU_USER_IDX 0 @@ -2100,7 +2105,11 @@ static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) { - return mmu_idx | ARM_MMU_IDX_A; + if (arm_feature(env, ARM_FEATURE_M)) { + return mmu_idx | ARM_MMU_IDX_M; + } else { + return mmu_idx | ARM_MMU_IDX_A; + } } /* Return the exception level we're running at if this is our mmu_idx */ @@ -2109,6 +2118,8 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { case ARM_MMU_IDX_A: return mmu_idx & 3; + case ARM_MMU_IDX_M: + return mmu_idx & 1; default: g_assert_not_reached(); } @@ -2119,6 +2130,12 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) { int el = arm_current_el(env); + if (arm_feature(env, ARM_FEATURE_M)) { + ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; + + return arm_to_core_mmu_idx(mmu_idx); + } + if (el < 2 && arm_is_secure_below_el3(env)) { return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 520adcc..791332c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6992,6 +6992,8 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1SE1: case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUser: return 1; default: g_assert_not_reached(); @@ -7008,6 +7010,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1E2: case ARMMMUIdx_S2NS: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUser: return false; case ARMMMUIdx_S1E3: case ARMMMUIdx_S1SE0: @@ -7146,6 +7150,7 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_MUser: return true; default: return false; diff --git a/target/arm/translate.c b/target/arm/translate.c index 8d509a2..ac905dd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -161,6 +161,9 @@ static inline int get_a32_user_mem_index(DisasContext *s) case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE1: return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); + case ARMMMUIdx_MUser: + case ARMMMUIdx_MPriv: + return arm_to_core_mmu_idx(ARMMMUIdx_MUser); case ARMMMUIdx_S2NS: default: g_assert_not_reached();