From patchwork Thu Jul 27 10:59:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 108824 Delivered-To: patches@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1891397qge; Thu, 27 Jul 2017 03:59:13 -0700 (PDT) X-Received: by 10.28.34.130 with SMTP id i124mr2854737wmi.137.1501153153760; Thu, 27 Jul 2017 03:59:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501153153; cv=none; d=google.com; s=arc-20160816; b=oiTPnD+fSBlWe13dvPvLKO9J3YZFSkFBt+wVougWQoZw1gZnDCRhS5HAiT4g5F0KUg A+atp/yY3Fjj0guJtMq3ZjXjKk3+V9gzjMMrOJh3uLvoGPg2KPN+rriMe2FGsdZ8sZar CUDciWzP00VqgrdM52SZ2g77avWDsVUpYD39CjHreOBkKpQVFNoMARholLofu2S6a+xy 42RRAKUxCCrdro0GfM+x2sztjk7P1TAT/UHRK5jYReR1Y+smav1hJIEXj+yXokIfPIoR DjvhJ/IRVH0uj2ZdiseQ44yDo0ZRCzLXEzN4H/ExhrPnfvVpImr0j0ykD9VZkwy5/y2a lJuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=0P1+p/ybu7yRPhxKGm8K2Ws7peRvbF3x0dxJfEYdif8=; b=e38DQfPKhuZB0aruCETSXMfZ6WitqnvXIuShqrrC6HAqVRbydWtp7E9JtkozFLb8FM b4mxPfCsoW5Ew7zHWDMoV15/SrxvdbxvjnRzXCdHonq7Om4FHBH2JKSN3z5F8/uCtYgx /04p1ekKb9vrG4dNmQbkIQ3cZ79YAeVM5koxRmjqPrFZB7AP+AsCgkF7cI/PVSC0wH/N 7KihrOZQvaMYtEi69mLE7IZOdNiUObOOeEj1wZc0/QvEs74F/JrbAF3rGYSGISdSligD PIInlltIv8z4Ktp+MU+ym8Rv6lWNbhbynKIH21Sna2xybDdeiM5/uedpi+m9q8vXjHJx lVMQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 141si10965509wmo.213.2017.07.27.03.59.13 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Jul 2017 03:59:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dagVd-0003mN-9k; Thu, 27 Jul 2017 11:59:13 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH for-2.10 4/5] target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset Date: Thu, 27 Jul 2017 11:59:09 +0100 Message-Id: <1501153150-19984-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> References: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> When the PMSAv7 implementation was originally added it was for R profile CPUs only, and reset was handled using the cpreg .resetfn hooks. Unfortunately for M profile cores this doesn't work, because they do not register any cpregs. Move the reset handling into arm_cpu_reset(), where it will work for both R profile and M profile cores. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 14 ++++++++++++++ target/arm/helper.c | 28 ++++++++++++---------------- 2 files changed, 26 insertions(+), 16 deletions(-) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 96d1f84..05c038b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -232,6 +232,20 @@ static void arm_cpu_reset(CPUState *s) env->vfp.xregs[ARM_VFP_FPEXC] = 0; #endif + + if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V7)) { + if (cpu->pmsav7_dregion > 0) { + memset(env->pmsav7.drbar, 0, + sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); + memset(env->pmsav7.drsr, 0, + sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); + memset(env->pmsav7.dracr, 0, + sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + } + env->pmsav7.rnr = 0; + } + set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status); diff --git a/target/arm/helper.c b/target/arm/helper.c index 63187de..a9247e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2404,18 +2404,6 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, *u32p = value; } -static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu = arm_env_get_cpu(env); - uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); - - if (!u32p) { - return; - } - - memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); -} - static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2433,22 +2421,30 @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, } static const ARMCPRegInfo pmsav7_cp_reginfo[] = { + /* Reset for all these registers is handled in arm_cpu_reset(), + * because the PMSAv7 is also used by M-profile CPUs, which do + * not register cpregs but still need the state to be reset. + */ { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), - .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, + .readfn = pmsav7_read, .writefn = pmsav7_write, + .resetfn = arm_cp_reset_ignore }, { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, .access = PL1_RW, .type = ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), - .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, + .readfn = pmsav7_read, .writefn = pmsav7_write, + .resetfn = arm_cp_reset_ignore }, { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, .access = PL1_RW, .type = ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), - .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, + .readfn = pmsav7_read, .writefn = pmsav7_write, + .resetfn = arm_cp_reset_ignore }, { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, pmsav7.rnr), - .writefn = pmsav7_rgnr_write }, + .writefn = pmsav7_rgnr_write, + .resetfn = arm_cp_reset_ignore }, REGINFO_SENTINEL };