From patchwork Thu Jul 27 10:59:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 108825 Delivered-To: patches@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1891404qge; Thu, 27 Jul 2017 03:59:14 -0700 (PDT) X-Received: by 10.28.16.17 with SMTP id 17mr2764032wmq.1.1501153154248; Thu, 27 Jul 2017 03:59:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501153154; cv=none; d=google.com; s=arc-20160816; b=LdAnrgWOykFMnVS0hYTv2StfwrwB9ZX1IrzLBcijizTTavQn71OsxU58aLv3+0wYCl YTetsjpjbrSxSnYc1D7EhaHLl8zzGav2Ct2WHbiutbjnCASIlrPH5oIkmxiAsIJwvMJf 0l9w56RKgFRVjMYGgNXsqdzjwqgZnRVPpjFx5V55liJp1lx6ko9Jl3YtPAVE0qn5vbNz FnjuKY6CEY2X8cY8ZsudLVRpiLksxfqgdbJOuOhOktGRvRO9Okb3Wog003FduYmy5uaW yyDgFDT598jrQ6nUbQUwWWUUDAL7kdeI3F6kyPs6SoBjBe+mzk3353WMgzeItXZjew68 VfCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=VYkTck1B6RSvtTY+92obNsXIkM/EqnfVZoNwI/Eaxyo=; b=LmPlXQXgOBCTIFZNvqgaGfKvCvGXqYCyPrG1j4gLq2/BMGQ3KZj5SLkLuLAw+eSEG8 yLiKRVBfzgzXSaVD5bWy5QcdT6zgLPfr0K4lSwH5Ebd8wyazHB8zwCObO9SSWk3IhIPL U9t8xd6fyhpVjt4GzUocCQrRxsdWRLpIRljKJZWuFYN5jMC9bDTWfLimGhB4x+KaHIo6 3iwbqjuwVkREoLclqz1YoK8KvHX4i+Qfe5yeGDpAXtXIaLTcQiQjXmVn6H9QyJ9/urMi s2JrD6wCcZVxShQPZdr6K2VbUDnDlclQTXtz5GVYSUwttSkfpcDZad0iVwI8vkdNvgHk FSMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id v16si14940157wrv.485.2017.07.27.03.59.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Jul 2017 03:59:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dagVd-0003ml-Pd; Thu, 27 Jul 2017 11:59:13 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH for-2.10 5/5] target/arm: Migrate MPU_RNR register state for M profile cores Date: Thu, 27 Jul 2017 11:59:10 +0100 Message-Id: <1501153150-19984-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> References: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> The PMSAv7 region number register is migrated for R profile cores using the cpreg scheme, but M profile doesn't use cpregs, and so we weren't migrating the MPU_RNR register state at all. Fix that by adding a migration subsection for the M profile case. Signed-off-by: Peter Maydell --- target/arm/machine.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/machine.c b/target/arm/machine.c index 93c1a78..1f66da4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -171,6 +171,29 @@ static const VMStateDescription vmstate_pmsav7 = { } }; +static bool pmsav7_rnr_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + /* For R profile cores pmsav7.rnr is migrated via the cpreg + * "RGNR" definition in helper.h. For M profile we have to + * migrate it separately. + */ + return arm_feature(env, ARM_FEATURE_M); +} + +static const VMStateDescription vmstate_pmsav7_rnr = { + .name = "cpu/pmsav7-rnr", + .version_id = 1, + .minimum_version_id = 1, + .needed = pmsav7_rnr_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { @@ -377,6 +400,11 @@ const VMStateDescription vmstate_arm_cpu = { &vmstate_iwmmxt, &vmstate_m, &vmstate_thumb2ee, + /* pmsav7_rnr must come before pmsav7 so that we have the + * region number before we test it in the VMSTATE_VALIDATE + * in vmstate_pmsav7. + */ + &vmstate_pmsav7_rnr, &vmstate_pmsav7, NULL }