From patchwork Wed Aug 2 16:43:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109261 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003390qge; Wed, 2 Aug 2017 09:44:08 -0700 (PDT) X-Received: by 10.99.116.26 with SMTP id p26mr22667499pgc.446.1501692248036; Wed, 02 Aug 2017 09:44:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692248; cv=none; d=google.com; s=arc-20160816; b=DuxGtl9U5HF1ZN47Hg+4a6Ck7F25Ckmq/1nKk6NMQCleXc5zDO6F9cOqf/FUxWsoeK wnqwpgWDnPwTub2tGpxWGebdr332N24jrN/lCaPkRJ3BVmPVbD4AJxsaWIR4JdySncmu 1YvmQRF2TRa183FYzKpFuRm5ETL3QRF5Td7chOWoC7enrzLFJWEqcTk2VLeAZsb0OdYD HU1ivqtMgQ/WdxDRGeZIUvCg3QQnj7ha09neXGIR7j4JWBU8BzQx1LBn24BN0Vx0V1z9 8PJzQNnfTFmYWOAmL9SbcJkJCV1axqY91NvIjypPgtDCxGME5Pv6CIFTmRH2kmhuy0F1 9uLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=TGpe+gwZK1tiZZ/w7896S24yO2koBdo3Pa1UR+C9wt8=; b=ObzmJr98um4p0EDZ8OEGaJI6YT8f1Ev9pLqWUf3DYtEXpRmN3PqUrffnL1JmsBjpvO cUpW4hnLYcjrHHaD321r4iTWbHsFUcI1QCRgcLoLmthamdp1i+GUDg6Z+exI6yp/3mbt w0RpQ4vA9IDQ/qNnl5uDB0E3KGpMtMxuDM+2SWUFWYL74YrXkGjhcJ1rHrkvhCYV/GXg XNenRTRbyn1XSqfNjUiXkIkI7Mx3PHL81zrCdpP9cWoXPQODXzOq9CA+fLko8gYnFP/8 jBaMKHz+INGwgMCUF/s3fdqWAuNLNZoCfjlnvUBHFuiL/H8jhOad9pkrKeWuNoiNiBfg tmGw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id b77si14351739pfb.525.2017.08.02.09.44.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkd-0003wR-EG; Wed, 02 Aug 2017 17:44:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 02/15] target/arm: Don't trap WFI/WFE for M profile Date: Wed, 2 Aug 2017 17:43:48 +0100 Message-Id: <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> M profile cores can never trap on WFI or WFE instructions. Check for M profile in check_wfx_trap() to ensure this. The existing code will do the right thing for v7M cores because the hcr_el2 and scr_el3 registers will be all-zeroes and so we won't attempt to trap, but when we start setting ARM_FEATURE_V8 for v8M cores the v8A handling of SCTLR.nTWE and .nTWI will not give the right results. Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2a85666..5a94a5f 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -370,6 +370,11 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) int cur_el = arm_current_el(env); uint64_t mask; + if (arm_feature(env, ARM_FEATURE_M)) { + /* M profile cores can never trap WFI/WFE. */ + return 0; + } + /* If we are currently in EL0 then we need to check if SCTLR is set up for * WFx instructions being trapped to EL1. These trap bits don't exist in v7. */