From patchwork Wed Aug 2 16:43:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109247 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003333qge; Wed, 2 Aug 2017 09:44:04 -0700 (PDT) X-Received: by 10.28.154.211 with SMTP id c202mr4055815wme.91.1501692244417; Wed, 02 Aug 2017 09:44:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692244; cv=none; d=google.com; s=arc-20160816; b=aoFsyYTjU3rzwrCrgN0Mnj5uqtABCqmEUK5Gj/VdWAtZUN6xiBLkLgteqoCAyEhygy CeSCYC3FSu9G12oCvmJrN9u4VfJ6bmkZjaxeHLKOJas1FoH4utztGHiBk8OG9botDi+3 J/SKPIHI2fEYrwK5x3ymKxUaJQJLaIYjquYqxsP+fdyhI+e/d56OawoLeciD++Z6thQx T8XsI8Msi59y5xnEd4oBPBZ7m0qnyiW87OnSvq+dLVIJ5rlurGOtGqKaEOHgh5sWn1fo PJ2BdH7KiStSS4QShNB8Lk1JSM9/HERefXk8nRXnU20GB5O/guGu/LpK7QCLgKAmp09U fJxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=b3ociU29Pzft7LUQDdFeYPohaoeo3n/FbHFN5KRptYc=; b=xIaZqlFqhDUW4gKzwNlV93t5AJTnHUsqV7p7i2u49p7vTzfUAKjHpM80o2v0aXXa2m QG3o6gsf1M/MxzcoQgPT7tLDQnMDTxN9YnybmwFDZyESgv2SiqugSRhdlVOX9w6BBjj+ X/YrXpcYuTuQEv/SURMcrq0Ir8I6oQ1HUyt6ZZfTNvDuc4bIrOCv/TYkNPvICffnqc55 wh0YqVT+gWilqohv8XMGbjGIOKrgfX/IvmUo65DfMDNRPTDJzF3FZkOvMbD3WrttE3ta yE4k/NCDtSTNzJc8amaOXs+kfvxfF92y6xnr0iWCLFQrbPMpCIgP+IoqvCuY6gPjwFMq orJw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id g39si25157255wrd.149.2017.08.02.09.44.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkd-0003wq-SX; Wed, 02 Aug 2017 17:44:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 03/15] target/arm: Consolidate PMSA handling in get_phys_addr() Date: Wed, 2 Aug 2017 17:43:49 +0100 Message-Id: <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> Currently get_phys_addr() has PMSAv7 handling before the "is translation disabled?" check, and then PMSAv5 after it. Tidy this up by making the PMSAv5 code handle the "MPU disabled" case itself, so that we have all the PMSA code in one place. This will make adding the PMSAv8 code slightly cleaner, and also means that pre-v7 PMSA cores benefit from the MPU lookup logging that the PMSAv7 codepath had. Signed-off-by: Peter Maydell --- target/arm/helper.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index b78d277..fd83a21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8423,6 +8423,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, uint32_t base; bool is_user = regime_is_user(env, mmu_idx); + if (regime_translation_disabled(env, mmu_idx)) { + /* MPU disabled. */ + *phys_ptr = address; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return false; + } + *phys_ptr = address; for (n = 7; n >= 0; n--) { base = env->cp15.c6_region[n]; @@ -8572,16 +8579,20 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } } - /* pmsav7 has special handling for when MPU is disabled so call it before - * the common MMU/MPU disabled check below. - */ - if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; *page_size = TARGET_PAGE_SIZE; - ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); - qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 + + if (arm_feature(env, ARM_FEATURE_V7)) { + /* PMSAv7 */ + ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, + phys_ptr, prot, fsr); + } else { + /* Pre-v7 MPU */ + ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, + phys_ptr, prot, fsr); + } + qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", access_type == MMU_DATA_LOAD ? "reading" : (access_type == MMU_DATA_STORE ? "writing" : "execute"), @@ -8594,21 +8605,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, return ret; } + /* Definitely a real MMU, not an MPU */ + if (regime_translation_disabled(env, mmu_idx)) { - /* MMU/MPU disabled. */ + /* MMU disabled. */ *phys_ptr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size = TARGET_PAGE_SIZE; return 0; } - if (arm_feature(env, ARM_FEATURE_PMSA)) { - /* Pre-v7 MPU */ - *page_size = TARGET_PAGE_SIZE; - return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); - } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, page_size, fsr, fi);