From patchwork Fri Aug 4 17:20:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109439 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp2445810qge; Fri, 4 Aug 2017 10:20:54 -0700 (PDT) X-Received: by 10.223.134.180 with SMTP id 49mr2100403wrx.157.1501867254851; Fri, 04 Aug 2017 10:20:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501867254; cv=none; d=google.com; s=arc-20160816; b=uouRt+X+L1bD9x0gWrXM6VF1WAI2CU37mSLvnlc3mONzuRExumnjMRn8cGvhdTMgdF JOm6ROHZzBevv0uLZ7Aqwp0fyWG6+00dUatJxo+rOSuD+Ff2o2UWyWYsehhktCv/p+uA /ACgRuNUl7reTEpSaglunPDRrmWfaMcbxRDbJlY7fJM5KBzk/gYSljWQQAvIo/ENNe7u IK57Z91eLyju0njkhOsVumZqQeGtUGMrJK6mR9LmPwlSrnMrQ5LMJstyrggVDg1BhaFw OZ57iFwkMqxytiiCsgcLiUo/BXMvcDjL86L/5m/BpMDEMEKJ5arkkEJrlrFwixgoEIbV RCWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=W+RGmC9taOcvCwfyGEQmZT/QcbwUkHzPmeKzCV5QRKc=; b=fUJq4EMNCVSh8kvZNWB95TnMPAPhWqHeY59KUCPy9eP+2+HVEOzF33bArlygTDnQfW eOviScM1EKjmPG8ca6fBiG4HPMqRwlj92nDxiE/oaVrZZEvsRVFdzW3MOPB/ardCMmzy 9jypWtH0DIyvK0v4P5juiWqKd6T63ytMRToqEztNPIeFPtZwuH2smJPwJ1fi4lTmyxxr wWZ0TCRQfj/qFsaRmzirQtTQK54gxymFYTVdAivswKuccA8w16WquixNbOGZH1U7ZAfJ JPnYOGwjS25S8oJHUFide+Bg3TSpkJElAyw2yzI0Cjp99s94O080nvQs1+3Xa54I2yKN vSkA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 3si3882268wra.20.2017.08.04.10.20.54 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 10:20:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHO-0006uU-DU; Fri, 04 Aug 2017 18:20:54 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Subject: [PATCH 8/8] target/arm: Implement new do_transaction_failed hook Date: Fri, 4 Aug 2017 18:20:49 +0100 Message-Id: <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> Implement the new do_transaction_failed hook for ARM, which should cause the CPU to take a prefetch abort or data abort. Signed-off-by: Peter Maydell --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 1 + target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) -- 2.7.4 Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias diff --git a/target/arm/internals.h b/target/arm/internals.h index a3adbd8..13bb001 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -471,6 +471,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); +/* arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); + /* Call the EL change hook if one has been registered */ static inline void arm_call_el_change_hook(ARMCPU *cpu) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 05c038b..6baede0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1670,6 +1670,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #else cc->do_interrupt = arm_cpu_do_interrupt; cc->do_unaligned_access = arm_cpu_do_unaligned_access; + cc->do_transaction_failed = arm_cpu_do_transaction_failed; cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs = arm_asidx_from_attrs; cc->vmsd = &vmstate_arm_cpu; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 7eac272..54b6dd8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); } +/* arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint32_t fsr, fsc; + ARMMMUFaultInfo fi = {}; + ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); + + if (retaddr) { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); + } + + /* The EA bit in syndromes and fault status registers is an + * IMPDEF classification of external aborts. ARM implementations + * usually use this to indicate AXI bus Decode error (0) or + * Slave error (1); in QEMU we follow that. + */ + fi.ea = (response != MEMTX_DECODE_ERROR); + + /* The fault status register format depends on whether we're using + * the LPAE long descriptor format, or the short descriptor format. + */ + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { + /* long descriptor form, STATUS 0b010000: synchronous ext abort */ + fsr = (fi.ea << 12) | (1 << 9) | 0x10; + } else { + /* short descriptor form, FSR 0b01000 : synchronous ext abort */ + fsr = (fi.ea << 12) | 0x8; + } + fsc = 0x10; + + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); +} + #endif /* !defined(CONFIG_USER_ONLY) */ uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)