From patchwork Tue Aug 22 15:08:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 110677 Delivered-To: patches@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2816177qge; Tue, 22 Aug 2017 08:09:07 -0700 (PDT) X-Received: by 10.25.161.209 with SMTP id k200mr454834lfe.132.1503414547469; Tue, 22 Aug 2017 08:09:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503414547; cv=none; d=google.com; s=arc-20160816; b=MBnnd5c6e77w27YZw8JuKM/tQnpr6CvKEpjdXC95WT0tWQ2nYxJQbvnRgaDs/gaJWh +qXCMokxDrglZW9F2RppT6+E9GYuleyNdg1fjkJHLLBOVql/1zlZlpYBQOKBF9q4APUD Ww8e6wmaRLZrgXaI6kpQ4R0UpL59/iw/zy47m66J1m+GhUcgDf+4KD4REz9dJNROB7pp E7cwUQ/UP3dBAD4TrtZz1rMfqtcBi1EXJXkB5KgMWbiTTypj29rwMVFINEvrD8CS2Gps RelJujABez27lv3yoMCtHNP5UyWWusWrvibxemTvsFa/rdhqZpMKKoa4D7ozXSqLCHOw DtKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=n2uaVqbqUq5OlMflr5hz4owWhpu67v/nqAMNitJz9KA=; b=KWtlsAoCo6KbC3Hkga9odAMCBVkup1rFcRze6UWvZEYS9wNspH13XZIX+FjIWnMeev 3KXFxPIeurST9S5issmm7jqnjKuGliqAASP4gFEQPolZxu8YcKi1+3tIECjXwQnSq6xw +M1lpk3JjgqZxNmwCTHOHvDbBDZq3/0dq2lCN5m3fspXipvK6wgSHjhQeGajkSTvD4+d /MqK8w8peOccrqjlbFHsEDat8Bh7GLbGk9f4PUawcPQtaVJM4oEQEWTG8j42H4ixA1JB doU9/lXlD2Q6oTu+y+wpckb1aNNPwA0/itklJrVBXCQWC8wbQb2cUURxSfWW7FnotGRn 5WNA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id o10si1982944lfc.55.2017.08.22.08.09.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 08:09:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAni-0004in-99; Tue, 22 Aug 2017 16:09:06 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 12/20] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M Date: Tue, 22 Aug 2017 16:08:51 +0100 Message-Id: <1503414539-28762-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- hw/intc/armv7m_nvic.c | 8 ++++---- target/arm/cpu.c | 4 ++-- target/arm/machine.c | 6 ++++-- 4 files changed, 12 insertions(+), 10 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d0b0936..2f59828 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -545,8 +545,8 @@ typedef struct CPUARMState { */ uint32_t *rbar; uint32_t *rlar; - uint32_t mair0; - uint32_t mair1; + uint32_t mair0[2]; + uint32_t mair1[2]; } pmsav8; void *nvic; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 3a1f02d..e98eb95 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -604,12 +604,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { goto bad_offset; } - return cpu->env.pmsav8.mair0; + return cpu->env.pmsav8.mair0[attrs.secure]; case 0xdc4: /* MPU_MAIR1 */ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { goto bad_offset; } - return cpu->env.pmsav8.mair1; + return cpu->env.pmsav8.mair1[attrs.secure]; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); @@ -826,7 +826,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } if (cpu->pmsav7_dregion) { /* Register is RES0 if no MPU regions are implemented */ - cpu->env.pmsav8.mair0 = value; + cpu->env.pmsav8.mair0[attrs.secure] = value; } /* We don't need to do anything else because memory attributes * only affect cacheability, and we don't implement caching. @@ -838,7 +838,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } if (cpu->pmsav7_dregion) { /* Register is RES0 if no MPU regions are implemented */ - cpu->env.pmsav8.mair1 = value; + cpu->env.pmsav8.mair1[attrs.secure] = value; } /* We don't need to do anything else because memory attributes * only affect cacheability, and we don't implement caching. diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae866be..ae8af19 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -249,8 +249,8 @@ static void arm_cpu_reset(CPUState *s) } } env->pmsav7.rnr = 0; - env->pmsav8.mair0 = 0; - env->pmsav8.mair1 = 0; + memset(env->pmsav8.mair0, 0, sizeof(env->pmsav8.mair0)); + memset(env->pmsav8.mair1, 0, sizeof(env->pmsav8.mair1)); } set_flush_to_zero(1, &env->vfp.standard_fp_status); diff --git a/target/arm/machine.c b/target/arm/machine.c index cd6b6af..414a879 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -229,8 +229,8 @@ static const VMStateDescription vmstate_pmsav8 = { vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, vmstate_info_uint32, uint32_t), - VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), - VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -255,6 +255,8 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } };