From patchwork Tue Aug 22 15:08:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 110681 Delivered-To: patches@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2816273qge; Tue, 22 Aug 2017 08:09:11 -0700 (PDT) X-Received: by 10.28.153.14 with SMTP id b14mr577222wme.131.1503414551274; Tue, 22 Aug 2017 08:09:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503414551; cv=none; d=google.com; s=arc-20160816; b=O4qpmxqWIA14WB+/ghJqNZdUjX5uQk2S8GKbdBSqny5WVp3LjkqLgwLR7MWnadUSFW fQ42lH2I2fFyFjhSFGnXxiAMC1qOlRo7dfJGjHS5tye18sAO/GYalpSChNbvxda3YDxJ 8Ukb4JpW27oG/9HyYoRWalxjFgUr2w6F5Unoi+6m3HX+SBLhYcKltHG+xNZIMQT2s9w7 m7/lG+aTA+nXwH4vUIE1DpLZimsGnIy2FUO9M7bLHkWvj3eDlWae5wbMS6d0aGptVBLc CaF+Jq0Ds8mPItIf1EjjTZuB6VOmTsn9x/ZAIBwDCiSha9+um6TJmPB5/P8JymA4srdx E/Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=kE6xWZi2IMg4sT8d0R+McIWwziPSQ44v6M9kDzQFZN8=; b=m/e3oRQRWHFOGFSjFtXHnDOMw5pyRI60i+wtkKoBavXVTp/hmVtJ6ac7LdMQ0ONo0X Rcc+L7g/+hrU/DFL+As747UICm+ZjsyaEs6REXpFjRZdXsIPnctYJS6eyLkTy7qWOvz4 viWpgvCLo97ZMQAC6N/6zB47X6mwSrsx51IJ/T5QZ1N8jWs/0FYOiawSWLH/Le842o8W hGQ0IJzuvstb5woX6trOvPoGL+5emi11tBsLGHHI8nEwTtLK3mwCQDAm3QmkXfaPNkBa /vOEOE6SV/B59hGkfYegBiT7aXrR2G4BPgcYr8q3AAqIunkYzT/5gaSk6hNyWhZkVL7s YCmQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id b25si11316575wrc.374.2017.08.22.08.09.11 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 08:09:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnm-0004l3-5h; Tue, 22 Aug 2017 16:09:10 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 17/20] target/arm: Make MMFAR banked for v8M Date: Tue, 22 Aug 2017 16:08:56 +0100 Message-Id: <1503414539-28762-18-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> Make the MMFAR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/machine.c | 3 ++- 4 files changed, 7 insertions(+), 6 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 25ebf9e..21c68d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -427,7 +427,7 @@ typedef struct CPUARMState { uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar; /* MemManage Fault Address */ + uint32_t mmfar[2]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ unsigned mpu_ctrl[2]; /* MPU_CTRL */ int exception; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index f071649..99b62ac 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -506,7 +506,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xd30: /* Debug Fault Status. */ return cpu->env.v7m.dfsr; case 0xd34: /* MMFAR MemManage Fault Address */ - return cpu->env.v7m.mmfar; + return cpu->env.v7m.mmfar[attrs.secure]; case 0xd38: /* Bus Fault Address. */ return cpu->env.v7m.bfar; case 0xd3c: /* Aux Fault Status. */ @@ -723,7 +723,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, cpu->env.v7m.dfsr &= ~value; /* W1C */ break; case 0xd34: /* Mem Manage Address. */ - cpu->env.v7m.mmfar = value; + cpu->env.v7m.mmfar[attrs.secure] = value; return; case 0xd38: /* Bus Fault Address. */ cpu->env.v7m.bfar = value; diff --git a/target/arm/helper.c b/target/arm/helper.c index 28b3d6c..e587e85 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6380,10 +6380,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case EXCP_DATA_ABORT: env->v7m.cfsr |= (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); - env->v7m.mmfar = env->exception.vaddress; + env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, "...with CFSR.DACCVIOL and MMFAR 0x%x\n", - env->v7m.mmfar); + env->v7m.mmfar[env->v7m.secure]); break; } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); diff --git a/target/arm/machine.c b/target/arm/machine.c index 4457ec6..5122e58 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -121,7 +121,7 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), - VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), + VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.bfar, ARMCPU), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), @@ -272,6 +272,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } };