From patchwork Tue Aug 22 15:08:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 110667 Delivered-To: patches@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2815971qge; Tue, 22 Aug 2017 08:09:00 -0700 (PDT) X-Received: by 10.28.6.212 with SMTP id 203mr604235wmg.126.1503414540119; Tue, 22 Aug 2017 08:09:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503414540; cv=none; d=google.com; s=arc-20160816; b=egzyksgqAwYx9/QEh4yNEO8qStaWtfdoUifJqs8brwoEP7VXkvvTfLfQ75lxtci3AI q2xqt6PAR7Al77muvdgaSMYSiM5Vxp/wVq42CS3tG6UxOmvXCHXi5smDeIrRaLTWsUjR RTffHSLtXOQS67BV4dVHgCjlW6HnxtUfZRowUnD51G/MR6QthIApv+fbmLjJoZVreIic ZHmv8jYARC/fY+HyaTTaar6hk7RI28/M+uLsQSU21K2zyO6qyJ3NJ6Yv7nMsXzUwnpGX lWnNEN/8bPHXFjADrHmWnbmIgOzDu7540OIj6ciTA2+njib84+6dUdAuUtva/l95oGAd 5B4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=5nzO7zo8161xQHIbcIVqfq8W0ywj5SWr6gWM8Cdjp2E=; b=0i65Q57omXls8YGea6jaAZ3OGmdIguEbdQMvQHPlSuLGK30mSaKoOtEOwug5/RjA1n oBsX5Qm5uKbvI9FOS6sQqTSvmbT7IqzIc45Y9PMNOuM2bRYOk7G9x+V+KWo142l1XAWA zQxtDxoD5mKeaxhedBKELvVcg/ohOlH14xYybh7U1NvcfH+MV5grvRP5Kb37h142foGa ciIOZHKe5b7EQGiJ5APCfADIdJ2tqlJappPPmo9Ia6bzPNPNzxlH/gpWoZznODdNiaAF bf2KREqdcAdia6YKK5rwyLKaemLA+DPtykB4i6up0ORgooZUZhbcq2sxMbcUZpuTKYnH O+FA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id x42si11577263wrb.449.2017.08.22.08.08.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 08:09:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnb-0004eF-6B; Tue, 22 Aug 2017 16:08:59 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 03/20] target/arm: Add state field, feature bit and migration for v8M secure state Date: Tue, 22 Aug 2017 16:08:42 +0100 Message-Id: <1503414539-28762-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> As the first step in implementing ARM v8M's security extension: * add a new feature bit ARM_FEATURE_M_SECURITY * add the CPU state field that indicates whether the CPU is currently in the secure state * add a migration subsection for this new state (we will add the Secure copies of banked register state to this subsection in later patches) * add a #define for the one new-in-v8M exception type * make the CPU debug log print S/NS status Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 +++ target/arm/cpu.c | 4 ++++ target/arm/machine.c | 20 ++++++++++++++++++++ target/arm/translate.c | 8 +++++++- 4 files changed, 34 insertions(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b6bb78a..24666baa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -66,6 +66,7 @@ #define ARMV7M_EXCP_MEM 4 #define ARMV7M_EXCP_BUS 5 #define ARMV7M_EXCP_USAGE 6 +#define ARMV7M_EXCP_SECURE 7 #define ARMV7M_EXCP_SVC 11 #define ARMV7M_EXCP_DEBUG 12 #define ARMV7M_EXCP_PENDSV 14 @@ -420,6 +421,7 @@ typedef struct CPUARMState { int exception; uint32_t primask; uint32_t faultmask; + uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; /* Information associated with an exception about to be taken: @@ -1264,6 +1266,7 @@ enum arm_features { ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ + ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8b610de..f32317e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -185,6 +185,10 @@ static void arm_cpu_reset(CPUState *s) uint32_t initial_pc; /* Loaded from 0x4 */ uint8_t *rom; + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + env->v7m.secure = true; + } + /* The reset value of this bit is IMPDEF, but ARM recommends * that it resets to 1, so QEMU always does that rather than making * it dependent on CPU model. diff --git a/target/arm/machine.c b/target/arm/machine.c index 05e2909..745adae 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -235,6 +235,25 @@ static const VMStateDescription vmstate_pmsav8 = { } }; +static bool m_security_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + return arm_feature(env, ARM_FEATURE_M_SECURITY); +} + +static const VMStateDescription vmstate_m_security = { + .name = "cpu/m-security", + .version_id = 1, + .minimum_version_id = 1, + .needed = m_security_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.v7m.secure, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { @@ -484,6 +503,7 @@ const VMStateDescription vmstate_arm_cpu = { */ &vmstate_pmsav7_rnr, &vmstate_pmsav7, + &vmstate_m_security, NULL } }; diff --git a/target/arm/translate.c b/target/arm/translate.c index e52a6d7..dea0a6f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12232,6 +12232,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, if (arm_feature(env, ARM_FEATURE_M)) { uint32_t xpsr = xpsr_read(env); const char *mode; + const char *ns_status = ""; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + ns_status = env->v7m.secure ? "S " : "NS "; + } if (xpsr & XPSR_EXCP) { mode = "handler"; @@ -12243,13 +12248,14 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } } - cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n", + cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", xpsr, xpsr & XPSR_N ? 'N' : '-', xpsr & XPSR_Z ? 'Z' : '-', xpsr & XPSR_C ? 'C' : '-', xpsr & XPSR_V ? 'V' : '-', xpsr & XPSR_T ? 'T' : 'A', + ns_status, mode); } else { uint32_t psr = cpsr_read(env);