From patchwork Tue Aug 22 15:08:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 110668 Delivered-To: patches@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2816011qge; Tue, 22 Aug 2017 08:09:01 -0700 (PDT) X-Received: by 10.28.99.138 with SMTP id x132mr8821wmb.58.1503414541175; Tue, 22 Aug 2017 08:09:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503414541; cv=none; d=google.com; s=arc-20160816; b=usaGl4Kj6NX2Z654PRz6e6R93cAgQqy501iRATy2Zk2TOAfPoPXJJJgqtxRNACqNEq EY2EbKly6wLRcvgqEARk6zQ+kKXedkbLjsESew38ZAx/Yfy5VUkJ9G6jxUAoTdiSEq1U hbbXhZV8h52dctnnUMv//Nb8fjWGu7mVGbXq42ayWiEe8Sz3DeCxvbsnp4Mi+iMUHyBu jvKTZ5wCxPWD1Kkv4HncUIPTvqzxW7GMYEgYgZst3eQx3iwIKdgEhipMPJK96yplB1kU sLzH+gneK+fBhhpVGK8G6GB2lN/eRDdnfoli94e4Vkr3N8Gm4WeoiYyNZ1ywO8/XjGjb Xs2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=2wRUDHW6BYy8nSk4IUjGsZPqQgyPdoimScGQ2jae2Yk=; b=puCG11doeshzKDFv9KHEvTODDms6rQTHIyWt2G1DU0hgIy2Wzu5rzrnpAu5zgcd6rr 8MUzHJvWD9GsTY+mBblxVCY9wIILjPA3n2ojY26Umc1LVq1OlBqg7EsQpaRNh/92W9qi oLIYVm0FdQUjBrBabtNKFDvRLdTe/ROgmafZ+K6i1/vDpzRPj6yySzrAOfvpuHSfb2eg BIvy2qF3RY8vD//V569zsL7Ab98atOyLluGDRu3rCroYQ4xfc+o0a3viA42ncHuHm3QB q1teABq2B15+/23bCEpAnVo/4vRXU6tzcXvxElY0e5SAKderNHVGL681C8Xwa6dtYvKg WVsA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id k184si57075wme.87.2017.08.22.08.09.00 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 08:09:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnc-0004eU-4e; Tue, 22 Aug 2017 16:09:00 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 04/20] target/arm: Register second AddressSpace for secure v8M CPUs Date: Tue, 22 Aug 2017 16:08:43 +0100 Message-Id: <1503414539-28762-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> If a v8M CPU supports the security extension then we need to give it two AddressSpaces, the same way we do already for an A profile core with EL3. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f32317e..ae866be 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -843,22 +843,21 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) init_cpreg_list(cpu); #ifndef CONFIG_USER_ONLY - if (cpu->has_el3) { - cs->num_ases = 2; - } else { - cs->num_ases = 1; - } - - if (cpu->has_el3) { + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { AddressSpace *as; + cs->num_ases = 2; + if (!cpu->secure_memory) { cpu->secure_memory = cs->memory; } as = address_space_init_shareable(cpu->secure_memory, "cpu-secure-memory"); cpu_address_space_init(cs, as, ARMASIdx_S); + } else { + cs->num_ases = 1; } + cpu_address_space_init(cs, address_space_init_shareable(cs->memory, "cpu-memory"),