From patchwork Tue Aug 22 15:08:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 110671 Delivered-To: patches@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2816076qge; Tue, 22 Aug 2017 08:09:03 -0700 (PDT) X-Received: by 10.25.215.104 with SMTP id o101mr365957lfg.24.1503414543417; Tue, 22 Aug 2017 08:09:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503414543; cv=none; d=google.com; s=arc-20160816; b=AJJTdabVuoDFPIBeCl1EPl4eg7pyraujSryUIbnFlaQhl5UbaJuLDbb5ok01cfOxlm C2ccCBvVBmE+P9Xo0NwARJl1Oc5ci1USn0cLAwJADAAyww0yqunAUnT6y7OPN7pJBqAR /PaG9Uv03liUYsyb587w++uWvJw3yDS6Eg0ahmWzAcSJppdipHwsAu9wIq/nLiOLqMZp v9qsXfBwFD41U1Amip/NKIuwpShCrxSqZ7lTQ0FWFJJeyJ3CEU/MmG0D8shbLYn4qy8+ sT0yw29ivL0gUChhIXOQjUFxJOMs2Ls94wOiBIu6sWdXFc0d/poIC6FulFNwhafXTC6F lyvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=i35px/cVwmZI7aAmHE1o6idhO6qXvbvULgKf75+1LEk=; b=nIBx7Ab7L0K0zSBvm2GHhvIpe4tQNbnu/nI+60TvHKYymPkykWW0/dSrdnlRZFotyt rs8PAXMin30w3P543T2S3FjpcBGKGcUXfZmpXoqPBFmK0dApxmlSRlV6IpycPKQ61n9l EXImgOTPI3Bys0LR1DGBX1D93L5bKS9vSLKgHMEwUdj2GUeBj/9C7qd9+8xqLl3wSngT wZ9oovUugtxtO7h9FrT3lTIXZPexrPgeuq/MiGnfh1wTKuemkrwIIVJ8cFsaPYZjmdkn w0+5xJ6BkwZuukvcEePBYtoh1rshUIUDtj8eiJWmcwbvI+EEFXyDjNokskOD1JjG5wlc iiiA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id u8si6071440ljd.174.2017.08.22.08.09.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 08:09:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAne-0004fz-9a; Tue, 22 Aug 2017 16:09:02 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 07/20] target/arm: Make PRIMASK register banked for v8M Date: Tue, 22 Aug 2017 16:08:46 +0100 Message-Id: <1503414539-28762-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> Make the PRIMASK register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to be restricted). Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 2 +- target/arm/helper.c | 4 ++-- target/arm/machine.c | 9 +++++++-- 4 files changed, 11 insertions(+), 6 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0c28dfd..fee337b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -431,7 +431,7 @@ typedef struct CPUARMState { uint32_t bfar; /* BusFault Address */ unsigned mpu_ctrl; /* MPU_CTRL */ int exception; - uint32_t primask; + uint32_t primask[2]; uint32_t faultmask; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2a41e5d..a654792 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -169,7 +169,7 @@ static inline int nvic_exec_prio(NVICState *s) if (env->v7m.faultmask) { running = -1; - } else if (env->v7m.primask) { + } else if (env->v7m.primask[env->v7m.secure]) { running = 0; } else if (env->v7m.basepri[env->v7m.secure] > 0) { running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); diff --git a/target/arm/helper.c b/target/arm/helper.c index 1087f19..c0a6dbd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8835,7 +8835,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? env->regs[13] : env->v7m.other_sp; case 16: /* PRIMASK */ - return env->v7m.primask; + return env->v7m.primask[env->v7m.secure]; case 17: /* BASEPRI */ case 18: /* BASEPRI_MAX */ return env->v7m.basepri[env->v7m.secure]; @@ -8895,7 +8895,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } break; case 16: /* PRIMASK */ - env->v7m.primask = val & 1; + env->v7m.primask[env->v7m.secure] = val & 1; break; case 17: /* BASEPRI */ env->v7m.basepri[env->v7m.secure] = val & 0xff; diff --git a/target/arm/machine.c b/target/arm/machine.c index 8476efd..6f0f6c9 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -103,7 +103,7 @@ static const VMStateDescription vmstate_m_faultmask_primask = { .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), - VMSTATE_UINT32(env.v7m.primask, ARMCPU), + VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -251,6 +251,7 @@ static const VMStateDescription vmstate_m_security = { .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.secure, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -271,9 +272,13 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, * differences are that the T bit is not in the same place, the * primask/faultmask info may be in the CPSR I and F bits, and * we do not want the mode bits. + * We know that this cleanup happened before v8M, so there + * is no complication with banked primask/faultmask. */ uint32_t newval = val; + assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); + newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); if (val & CPSR_T) { newval |= XPSR_T; @@ -287,7 +292,7 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, env->v7m.faultmask = 1; } if (val & CPSR_I) { - env->v7m.primask = 1; + env->v7m.primask[M_REG_NS] = 1; } val = newval; }