From patchwork Mon Sep 11 13:52:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112193 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825802pji; Mon, 11 Sep 2017 06:51:53 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5WDIlv2oVJKxYAqtruy8NSDIr/Es6IxMRioBARHlL9MmYiC3gYaffhp+YGktK2byHVocVu X-Received: by 10.98.157.74 with SMTP id i71mr12351689pfd.168.1505137912916; Mon, 11 Sep 2017 06:51:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137912; cv=none; d=google.com; s=arc-20160816; b=n84nPP1vPhDvhUar9JO8iT0UJE/ohCSkVd32XGXd9UeaNMt0Cqll7iFpgx8D2Hio0V saiU9Wb0Xbqk3nUhYg4TXMa7FbGaRpjzorhiXuBTraowFigtPL5Znd4OKRiCAzK6M1fm VbI/cDqEbap87Wug1auvhQsAFRx+Nv99rfhCBi49NlQkFdbpVp0jYNqWfA9e5C+tXkL5 xaO8A07dv1CoPGYfOr6VWhUQpPwJ0Dyf4iCjveMA5/F0CdrIz9EGQt1NW+6p3/cLqvjo COAbkfJDrBqUX4dJGfX0h0YA0qDWkza4UjqULvoJZ8LqCfvbk8vQTGGiLuzPlaw3Pl55 BMVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=OAQAEcY47GohXWNIe8wik0dL6owj/qwY92P7fleqBa4=; b=VvYghOcOj1UrdBYH5PM9tU/iRNlDszrAwsWxwTApIF7bts3mHzJhHEBWLVHCyPD6bw 0MLM3g/yP7PE+vaKIj4hdi7CoVq2PMwGloT13Bcra55uw3VivN7MtmktkVztXAa6nt/f /Y68Xb0pEmphOFtKO5jTDlEULsUdvD+bF05XWGXNVEfrPUA2aXYsd3nXCvKMhzwKVOvq Bxr3PlCgahP0B2dIx98TPbuNo0WR5tvW9O/Jai7SQW7jznyOo85s/YWXrcJRwc6hD9RC XJufiOaDPU7PP8h+VNdu1F+fWWng7NS73bi3+qPSNdikYYX9kB0h0DdjJWrgOntBQ2o5 uNlw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 92si6810776plw.40.2017.09.11.06.51.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7q-0007m1-6B; Mon, 11 Sep 2017 14:51:46 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 2/7] target/arm: Clear exclusive monitor on v7M reset, exception entry/exit Date: Mon, 11 Sep 2017 14:52:05 +0100 Message-Id: <1505137930-13255-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> For M profile we must clear the exclusive monitor on reset, exception entry and exception exit. We weren't doing any of these things; fix this bug. Signed-off-by: Peter Maydell --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 6 ++++++ target/arm/helper.c | 2 ++ target/arm/op_helper.c | 2 +- 4 files changed, 19 insertions(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index 5d7f24c..a315354 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -444,6 +444,16 @@ void arm_handle_psci_call(ARMCPU *cpu); #endif /** + * arm_clear_exclusive: clear the exclusive monitor + * @env: CPU env + * Clear the CPU's exclusive monitor, like the guest CLREX instruction. + */ +static inline void arm_clear_exclusive(CPUARMState *env) +{ + env->exclusive_addr = -1; +} + +/** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1acce3..412e94c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -235,6 +235,12 @@ static void arm_cpu_reset(CPUState *s) env->regs[15] = 0xFFFF0000; } + /* M profile requires that reset clears the exclusive monitor; + * A profile does not, but clearing it makes more sense than having it + * set with an exclusive access on address zero. + */ + arm_clear_exclusive(env); + env->vfp.xregs[ARM_VFP_FPEXC] = 0; #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 329e517..668e367 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6175,6 +6175,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr) armv7m_nvic_acknowledge_irq(env->nvic); switch_v7m_sp(env, 0); + arm_clear_exclusive(env); /* Clear IT bits */ env->condexec_bits = 0; env->regs[14] = lr; @@ -6354,6 +6355,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } /* Otherwise, we have a successful exception exit. */ + arm_clear_exclusive(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index d1bca46..6a60464 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1022,7 +1022,7 @@ void HELPER(exception_return)(CPUARMState *env) aarch64_save_sp(env, cur_el); - env->exclusive_addr = -1; + arm_clear_exclusive(env); /* We must squash the PSTATE.SS bit to zero unless both of the * following hold: