From patchwork Mon Sep 11 13:52:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112187 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825711pji; Mon, 11 Sep 2017 06:51:49 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7FysvbbDZ+otsAtWrYtDbBXSmjo3RA9QgqvaUwiuMzEGJR0Fq6aNkbut0Sy4a+iF2GItzO X-Received: by 10.223.135.102 with SMTP id 35mr8552215wrz.160.1505137909500; Mon, 11 Sep 2017 06:51:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137909; cv=none; d=google.com; s=arc-20160816; b=iy4YgApt0Rqq1DrwWGqymgom3BFe2KR77QSguxVWFM4m+Evt2wnC+WQtXPiUBNy7dI QBpTXWNH20HtrhtGl+nqnCNzYRDiaaBXuCucrxq3tIY162e3tBoQJxgxUP5xH7mToaFd jh1m28miqjhxByTLIP1Rma//GmT8YgVze+fsP9YKcaIST1LzYLewPadP2/WiFCRiMZ2z Eh3pu7EeCYrVhWeSHdFo+mQdeiJhYOW4JlXSPiWKUPpF+rG6+CSCrPvI8FKlH+CKQgga f8U7Xj0AHQve6dkATZtwdGi17GdIqsSH8gn0UA+U106YLjbdv9Eg56l4im3PS5E7Sa/2 +GUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=TEbPFvKwynEH4nFWQ+8A95zks8NameeaaLUNU2P4XeA=; b=MKwjnS96z+CqcW9czG+bd23WG60Qb+4Uqj7n11o3bkfu09AvfcEBnEI7cdmeO+wgYL RJWJZ3AXOyOtXQJEK8D8UzXH4sKW1Jx3Um2DqI7Bz1Id8WkBwkfk/P4WZoJ+zx21GRWN AZozqE9fkx3kAfuoSbXEJ9GfKN1Ad5SbXgeKAEbnRE89jQ42FeSup2abc4jQL9HlePbf q12J9dHiFZB2iMNwKGG5xn/sPN65cxZcQiUzwc5IKXG8WOAtsBUfhb8s8K3GpgE/djJ3 nsXeepMTS80voVcg5BBB0OPCiNFz2wtkCIsC/stTeioChfCcyHFekLwy9d+Flxh3K1LP N72Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id s10si1681507wra.196.2017.09.11.06.51.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7r-0007mR-ID; Mon, 11 Sep 2017 14:51:47 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 4/7] nvic: Don't apply group priority mask to negative priorities Date: Mon, 11 Sep 2017 14:52:07 +0100 Message-Id: <1505137930-13255-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> In several places we were unconditionally applying the nvic_gprio_mask() to a priority value. This is incorrect if the priority is one of the fixed negative priority values (for NMI and HardFault), so don't do it. This bug would have caused both NMI and HardFault to be considered as the same priority and so NMI wouldn't correctly preempt HardFault. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1fecfd6..d3e2056 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -152,8 +152,12 @@ static void nvic_recompute_state(NVICState *s) } } + if (active_prio > 0) { + active_prio &= nvic_gprio_mask(s); + } + s->vectpending = pend_irq; - s->exception_prio = active_prio & nvic_gprio_mask(s); + s->exception_prio = active_prio; trace_nvic_recompute_state(s->vectpending, s->exception_prio); } @@ -329,7 +333,10 @@ void armv7m_nvic_acknowledge_irq(void *opaque) assert(vec->enabled); assert(vec->pending); - pendgroupprio = vec->prio & nvic_gprio_mask(s); + pendgroupprio = vec->prio; + if (pendgroupprio > 0) { + pendgroupprio &= nvic_gprio_mask(s); + } assert(pendgroupprio < running); trace_nvic_acknowledge_irq(pending, vec->prio);