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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id b45si8770476qtk.535.2017.09.14.11.04.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:04:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49248 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYVQ-0007L1-06 for patch@linaro.org; Thu, 14 Sep 2017 14:04:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJa-00085o-1A for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJZ-0007yS-0O for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJY-0007vb-Pf for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJT-0005rC-Aj for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:31 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:45 +0100 Message-Id: <1505411573-27848-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/18] xlnx-zcu102: Add a machine level secure property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add a machine level secure property. This defaults to false and can be set to true using this machine command line argument: -machine xlnx-zcu102,secure=on This follows what the ARM virt machine does. This property only applies to the ZCU102 machine. The EP108 machine does not have this property. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 2.7.4 diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 5b1f184..bd573c4 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -30,6 +30,8 @@ typedef struct XlnxZCU102 { XlnxZynqMPState soc; MemoryRegion ddr_ram; + + bool secure; } XlnxZCU102; #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") @@ -42,6 +44,20 @@ typedef struct XlnxZCU102 { static struct arm_boot_info xlnx_zcu102_binfo; +static bool zcu102_get_secure(Object *obj, Error **errp) +{ + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + return s->secure; +} + +static void zcu102_set_secure(Object *obj, bool value, Error **errp) +{ + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + s->secure = value; +} + static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) { int i; @@ -69,6 +85,8 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram), "ddr-ram", &error_abort); + object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", + &error_fatal); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); @@ -134,6 +152,10 @@ static void xlnx_ep108_init(MachineState *machine) static void xlnx_ep108_machine_instance_init(Object *obj) { + XlnxZCU102 *s = EP108_MACHINE(obj); + + /* EP108, we don't support setting secure */ + s->secure = false; } static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) @@ -169,6 +191,16 @@ static void xlnx_zcu102_init(MachineState *machine) static void xlnx_zcu102_machine_instance_init(Object *obj) { + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + /* Default to secure mode being disabled */ + s->secure = false; + object_property_add_bool(obj, "secure", zcu102_get_secure, + zcu102_set_secure, NULL); + object_property_set_description(obj, "secure", + "Set on/off to enable/disable the ARM " + "Security Extensions (TrustZone)", + NULL); } static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)