From patchwork Fri Sep 22 14:59:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 114035 Delivered-To: patches@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3394787qgf; Fri, 22 Sep 2017 07:59:31 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCJGyLzTYhsp+Qal2IJ5szxOUblrn1+Y9fn5HjJ/v3OrX2BK+7AL8bRUm5pq5+aZaR2y/oa X-Received: by 10.46.9.80 with SMTP id 77mr1456968ljj.54.1506092371866; Fri, 22 Sep 2017 07:59:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506092371; cv=none; d=google.com; s=arc-20160816; b=k2zYjbiWK6Fk3jHeu3z4xPi2fiyaQlI5LuJn+lp2pUKtJ7eyoouAJfr1EUzrXWha31 ozjQ7bpGlb6S3zwLgCDyK3pJQF1zbF9NoIH6xibeVNaGjnOsyYaqmdDmVzygc53Ie18x Zqe5tiYrIaJrEwRUCscIj5khqqw5mIFZ8bwp3/7IJcqttMO8S6jrJhgh096WB2Xh5Jer QYpIqBzuhIMgvmbmxDZ3Bab2M+KgCIjTT8rEXEKM76eW9YCmTPjww+PptXqfrw7oqo0C gAQUNh4ohornS3LS/+HeEXw1OoUVvjzPX2vvqyyn9O1ANIgvjafcPQdnEocgiiVR67uY FYNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=eYjzFvsOeZ7TOJ9PjbfOpFu+JiyM+T227XmUcJoz6dk=; b=B9VLXZIa9yIW0EJzDQwIQFdJRottRTQfxeZUwUOxdFbpSEBzpkgc3pl5jiOSkmNga+ s/ib2S5Ph3o8kkv+Plegiy++EcVZSwaOQBcTonoieOAPDvYlJZ0zp1ZtnI8yrGiLrwIV lruK/bB2hYkRowY69TSNumZygiiz3LiugGunwonyCNWAP5bFW6fzUXuYKg1aU3ezoZDT 7DSYQtrW2fA6A8WNLK8veafLGBHpH7BOkctRp/id+dRJFwS4UzJjUyu0vRmus0lFY7kb aD2e1WSKe6dDK+8nyph2g6w/zpC5Db9jcjThv0uXHckc/U2+UIoH97sttYNr/bZ6dyJK c8Dg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 65si6913lfp.343.2017.09.22.07.59.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Sep 2017 07:59:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dvPQQ-00077x-HY; Fri, 22 Sep 2017 15:59:30 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset Date: Fri, 22 Sep 2017 15:59:48 +0100 Message-Id: <1506092407-26985-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506092407-26985-1-git-send-email-peter.maydell@linaro.org> References: <1506092407-26985-1-git-send-email-peter.maydell@linaro.org> Reset for devices does not include an automatic clear of the device state (unlike CPU state, where most of the state structure is cleared to zero). Add some missing initialization of NVIC state that meant that the device was left in the wrong state if the guest did a warm reset. (In particular, since we were resetting the computed state like s->exception_prio but not all the state it was computed from like s->vectors[x].active, the NVIC wound up in an inconsistent state that could later trigger assertion failures.) Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index d90d8d0..bc7b66d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1782,6 +1782,11 @@ static void armv7m_nvic_reset(DeviceState *dev) int resetprio; NVICState *s = NVIC(dev); + memset(s->vectors, 0, sizeof(s->vectors)); + memset(s->sec_vectors, 0, sizeof(s->sec_vectors)); + s->prigroup[M_REG_NS] = 0; + s->prigroup[M_REG_S] = 0; + s->vectors[ARMV7M_EXCP_NMI].enabled = 1; /* MEM, BUS, and USAGE are enabled through * the System Handler Control register