diff mbox series

[5/9] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1

Message ID 1507556919-24992-6-git-send-email-peter.maydell@linaro.org
State Superseded
Headers show
Series v8M: BLXNS, SG, secure function return | expand

Commit Message

Peter Maydell Oct. 9, 2017, 1:48 p.m. UTC
The code which implements the Thumb1 split BL/BLX instructions
is guarded by a check on "not M or THUMB2". All we really need
to check here is "not THUMB2" (and we assume that elsewhere too,
eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).

This doesn't change behaviour because all M profile cores
have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
(v6M implements a very restricted subset of Thumb2, but we
can cross that bridge when we get to it with appropriate
feature bits.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/translate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

-- 
2.7.4

Comments

Richard Henderson Oct. 11, 2017, 12:29 a.m. UTC | #1
On 10/09/2017 06:48 AM, Peter Maydell wrote:
> The code which implements the Thumb1 split BL/BLX instructions

> is guarded by a check on "not M or THUMB2". All we really need

> to check here is "not THUMB2" (and we assume that elsewhere too,

> eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).

> 

> This doesn't change behaviour because all M profile cores

> have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.

> (v6M implements a very restricted subset of Thumb2, but we

> can cross that bridge when we get to it with appropriate

> feature bits.)

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  target/arm/translate.c | 3 +--

>  1 file changed, 1 insertion(+), 2 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~
diff mbox series

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 58d706c..f5ca87f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9722,8 +9722,7 @@  static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
     int conds;
     int logic_cc;
 
-    if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
-          || arm_dc_feature(s, ARM_FEATURE_M))) {
+    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
         /* Thumb-1 cores may need to treat bl and blx as a pair of
            16-bit instructions to get correct prefetch abort behavior.  */
         insn = insn_hw1;