From patchwork Tue Nov 28 14:35:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 119882 Delivered-To: patches@linaro.org Received: by 10.80.225.132 with SMTP id k4csp3165777edl; Tue, 28 Nov 2017 06:35:30 -0800 (PST) X-Google-Smtp-Source: AGs4zMZMZY7Jn5U8Z6gU8vEmmy3K6P2XlBemcq5mW6yoN2Cat0QmE9b9sLOCl5XJNSr2TZlKNC5j X-Received: by 10.46.41.68 with SMTP id u65mr18206136lje.47.1511879730365; Tue, 28 Nov 2017 06:35:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511879730; cv=none; d=google.com; s=arc-20160816; b=lsiOtZNtsmOK3K36bYhQNOqXgl+yOx6xvQtbr3bkbrZpLPkwO47pyNk8Yr/Qm2bdt/ bvyJ7FDgJsne5UJgJMweZNJQXadp/YYuP3Y6WImRiU++DxKmpV+OUdNuapOevOna0/VB HWgyfp2Nmu+jkvKMcjn40RqT1+6ua4sFI8hZXvaoAPqkKNiwwqViDg8zQ0mDFhzP5V/t ASOOBe2X05jCEzDk0lZX0Y6+8nvZ9rBaFmS8yS/AD3u66+yLC1mlDCL42VTVgFkNKZkJ 5R5mNz4TzHGabEUAtuEXrXRmzkUJlQRsys5zh1wMQhhbRjta9h0jtESVcrie5Sn6RtYR 47ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=gBtkRF6jNMa0s4/wr630zcu9h0FqqStUt2OpgdTtQ8s=; b=hL9KHWUvj9ukYFj7TD8XszUftNgexXh4BBivTXNtzjqvNiBPBX/QWWkJ0fVq3qwRSj 7JK4xGGToIg7nES+YHdfLiij5uAP2XkR4MWEIJZs0qeM5mG8R87c0NFKDqaOZF3Zk+UE HngxWIdmP5ZQATcOyz56T0PZvorL3N0fMWQbjOI6RinMOMZk6saQHawFnHsIwl+htXJG z0USp6m9YIVRwOwQ5PK3nrSF39eAoo9tj1opQlXv9liMMZznE3Z2nxbS/mK2s/eeQHZC sczNd/Zrr7+N7OIF2GqL9MBgnX8NbcU8PxE3LTm2SGuFt7dGmxA5YPDTB3V3Q0RkK9yh p8+g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id a200si1147492lfb.446.2017.11.28.06.35.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 28 Nov 2017 06:35:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eJgyt-00020d-Dg; Tue, 28 Nov 2017 14:35:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Richard Henderson , Riku Voipio , Laurent Vivier Subject: [PATCH 1/2] linux-user: Propagate siginfo_t through to handle_cpu_signal() Date: Tue, 28 Nov 2017 14:35:24 +0000 Message-Id: <1511879725-9576-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511879725-9576-1-git-send-email-peter.maydell@linaro.org> References: <1511879725-9576-1-git-send-email-peter.maydell@linaro.org> Currently all the architecture/OS specific cpu_signal_handler() functions call handle_cpu_signal() without passing it the siginfo_t. We're going to want that so we can look at the si_code to determine whether this is a SEGV_ACCERR access violation or some other kind of fault, so change the functions to pass through the pointer to the siginfo_t rather than just the si_addr value. Signed-off-by: Peter Maydell --- accel/tcg/user-exec.c | 39 ++++++++++++++------------------------- 1 file changed, 14 insertions(+), 25 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f42285e..e8f26ff 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -57,12 +57,13 @@ static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set) the effective address of the memory exception. 'is_write' is 1 if a write caused the exception and otherwise 0'. 'old_set' is the signal set which should be restored */ -static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, +static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, int is_write, sigset_t *old_set) { CPUState *cpu = current_cpu; CPUClass *cc; int ret; + unsigned long address = (unsigned long)info->si_addr; /* We must handle PC addresses from two different sources: * a call return address and a signal frame address. @@ -215,9 +216,8 @@ int cpu_signal_handler(int host_signum, void *pinfo, #endif pc = EIP_sig(uc); trapno = TRAP_sig(uc); - return handle_cpu_signal(pc, (unsigned long)info->si_addr, - trapno == 0xe ? - (ERROR_sig(uc) >> 1) & 1 : 0, + return handle_cpu_signal(pc, info, + trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, &MASK_sig(uc)); } @@ -261,9 +261,8 @@ int cpu_signal_handler(int host_signum, void *pinfo, #endif pc = PC_sig(uc); - return handle_cpu_signal(pc, (unsigned long)info->si_addr, - TRAP_sig(uc) == 0xe ? - (ERROR_sig(uc) >> 1) & 1 : 0, + return handle_cpu_signal(pc, info, + TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, &MASK_sig(uc)); } @@ -341,8 +340,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, is_write = 1; } #endif - return handle_cpu_signal(pc, (unsigned long)info->si_addr, - is_write, &uc->uc_sigmask); + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } #elif defined(__alpha__) @@ -372,8 +370,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, is_write = 1; } - return handle_cpu_signal(pc, (unsigned long)info->si_addr, - is_write, &uc->uc_sigmask); + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } #elif defined(__sparc__) @@ -432,8 +429,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, break; } } - return handle_cpu_signal(pc, (unsigned long)info->si_addr, - is_write, sigmask); + return handle_cpu_signal(pc, info, is_write, sigmask); } #elif defined(__arm__) @@ -466,9 +462,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, * later processor; on v5 we will always report this as a read). */ is_write = extract32(uc->uc_mcontext.error_code, 11, 1); - return handle_cpu_signal(pc, (unsigned long)info->si_addr, - is_write, - &uc->uc_sigmask); + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } #elif defined(__aarch64__) @@ -495,8 +489,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, void *puc) /* Ignore bits 23 & 24, controlling indexing. */ || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ - return handle_cpu_signal(pc, (uintptr_t)info->si_addr, - is_write, &uc->uc_sigmask); + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } #elif defined(__ia64) @@ -529,9 +522,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, void *puc) default: break; } - return handle_cpu_signal(ip, (unsigned long)info->si_addr, - is_write, - (sigset_t *)&uc->uc_sigmask); + return handle_cpu_signal(ip, info, is_write, (sigset_t *)&uc->uc_sigmask); } #elif defined(__s390__) @@ -583,8 +574,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, } break; } - return handle_cpu_signal(pc, (unsigned long)info->si_addr, - is_write, &uc->uc_sigmask); + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } #elif defined(__mips__) @@ -599,8 +589,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, /* XXX: compute is_write */ is_write = 0; - return handle_cpu_signal(pc, (unsigned long)info->si_addr, - is_write, &uc->uc_sigmask); + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } #else