From patchwork Tue Dec 5 19:46:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120745 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168224qgn; Tue, 5 Dec 2017 11:46:41 -0800 (PST) X-Google-Smtp-Source: AGs4zMbE0xDT+AvqfEzumGnLF3nbPlZXRLjZ+stdEoJJ8HXPnmXC6nyd//pFJmnG66oF4Rwylo81 X-Received: by 10.46.17.153 with SMTP id 25mr11890293ljr.36.1512503201335; Tue, 05 Dec 2017 11:46:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503201; cv=none; d=google.com; s=arc-20160816; b=NofuYHe3DCBQg2DKchYDOhebeVmcJNvkYYF5HaofYAPEspB3/G7QzD7NWUa4TgZemi oUhV4IoW6Q8WkbFzmMjbMMA0+4Gm8Tq4nSonlHxRESPP+rdmUAu+Pt0BWNCGAQUKrOwB Cs1UslQWf6Nko5bOiNO60KO0KCzTSQv4VzFWThmTy94YA0K6Oxx9HTZEvd4kHGiukpdp yJYA99oPpNgjW9kKfRTi5h/aGTTD/3ErNskBk+Ce+XGswtAf1u6YJ+ClvoZmfSUa6rzR kjRyDZMutJtdwbnIXJpX7EwQmge7nwnPgILhqGblmXE/nEWWH3c1/uXYFHvMuy9H1vNT tkkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=qB9RN9afNeI8kCNbWloE9IdDxroG41xi0OTHqDEVoV8=; b=LFCUrm2Jm0haItjJ61ObQOrFdqkq3k7RX4uyb21+xv+rb0BGec4avwNNu3fEcRfQWU svuIBVrE2iJ8R4nVr07koO6jsVvdCEP8b1SoM2/5Ssa9FJIHg8SsZr7BtDFPWK2ayZds EfkbLF6B+mtqgpkaeXb7K0ajeizrTwvNmun6QxpV0Rx7T3zR6R+imvMlLV3aD8yq+ORm LugXtLHfhFDppK0CMTc3spGH3+JaRV1072OxzbtkyddFTA2kyMODA7CXq+kpmfmCH0Cm BgGdH1AO4zRvgCizMpglQzz9TmoCQc+PyuF3UQG3+uqpZ4gBd7MvLrhZUni+eSXD61R+ PcgQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id s63si365293lja.82.2017.12.05.11.46.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAu-0005Ck-E7; Tue, 05 Dec 2017 19:46:40 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 10/12] target/arm: Ignore fsr from get_phys_addr() in do_ats_write() Date: Tue, 5 Dec 2017 19:46:30 +0000 Message-Id: <1512503192-2239-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> In do_ats_write(), rather than using the FSR value from get_phys_addr(), construct the PAR values using the information in the ARMMMUFaultInfo struct. This allows us to create a PAR of the correct format regardless of what the translation table format is. For the moment we leave the condition for "when should this be a 64 bit PAR" as it was previously; this will need to be fixed to properly support AArch32 Hyp mode. Signed-off-by: Peter Maydell --- target/arm/helper.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index fad4923..17192f8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2160,7 +2160,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, hwaddr phys_addr; target_ulong page_size; int prot; - uint32_t fsr; + uint32_t fsr_unused; bool ret; uint64_t par64; MemTxAttrs attrs = {}; @@ -2168,12 +2168,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, ARMCacheAttrs cacheattrs = {}; ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, - &prot, &page_size, &fsr, &fi, &cacheattrs); + &prot, &page_size, &fsr_unused, &fi, &cacheattrs); + /* TODO: this is not the correct condition to use to decide whether + * to report a PAR in 64-bit or 32-bit format. + */ if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { - /* fsr is a DFSR/IFSR value for the long descriptor - * translation table format, but with WnR always clear. - * Convert it to a 64-bit PAR. - */ + /* Create a 64-bit PAR */ par64 = (1 << 11); /* LPAE bit always set */ if (!ret) { par64 |= phys_addr & ~0xfffULL; @@ -2183,6 +2183,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ par64 |= cacheattrs.shareability << 7; /* SH */ } else { + uint32_t fsr = arm_fi_to_lfsc(&fi); + par64 |= 1; /* F */ par64 |= (fsr & 0x3f) << 1; /* FS */ /* Note that S2WLK and FSTAGE are always zero, because we don't @@ -2207,6 +2209,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= (1 << 9); /* NS */ } } else { + uint32_t fsr = arm_fi_to_sfsc(&fi); + par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | ((fsr & 0xf) << 1) | 1; }