From patchwork Tue Dec 5 19:46:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120739 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168146qgn; Tue, 5 Dec 2017 11:46:37 -0800 (PST) X-Google-Smtp-Source: AGs4zMZvzbQJK/Qceh6ENz1t0ZPaFe+aAdobt5ZHqHAnZaHfRkqF5EfRmDFeYtroMekQ4G4RFGYE X-Received: by 10.223.161.210 with SMTP id v18mr15924717wrv.170.1512503197522; Tue, 05 Dec 2017 11:46:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503197; cv=none; d=google.com; s=arc-20160816; b=SF/Ynlg95KLJnLCBaz6GsaEsiGPzefoUrcla528fbvchH0PqUdyiVlvR4+5R6HHWiD vFIXIATW3pxH+qNaeRahf5M+J9f8VSjblkGlPFQb6fIuGMUtkCT2xgeDn2HOwJutPjq5 iDgnrHvt3ySbUMLTSzrfUC/KEmNix8sLyxavLPTqPFRjVlwqicOkzPCkLIoP04XUEALk Com9DAMPiEDRTNmXod/1D2ZKOeMV5+5TfZPmmabV2hA7ryp1NuSXfx8FliYtU9L2BKcP v3s/UDESCZ8136KddCTv3j8dmf2Ed8n9Yr2cLkHwreDm7HATOo0/HIS9l2pU4JbGXzE3 zU2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=RSqqLoMHm8ToV87W23DTughwrSw0FE0JmhihawNa4NU=; b=UseSK77FL9vDShsqCfghbQFue6o8jautvQisrA1GTwnqkAAbzZB1armX41/SAAZHU8 yYNKHdr0LAtO0w1oyRJ5exx67J0uSzRdwt62cxZuCSWyXE9MidBcnKDhs6W4745MqMAa d96cz3BaxLSx/aVdLG35mVssBpKvsHdR3pRlOfPnpxmaMUKQ3xSPvTFi35WdiTTqWnG8 nHKFLNapbaUWqTByzcNj7ZME/5F3v0jJk9bjhl2LR6NUj4XvbLCTVSp7/IILcanDcne1 1rPqGDJtezF219F5DkMkC6iqMuvAfLagXC6rAyjfLKY3JWbMmMwb8rOUCr+6wHYlR4vi y9RA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 41si638004wrc.108.2017.12.05.11.46.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAq-0005AF-U6; Tue, 05 Dec 2017 19:46:36 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 05/12] target/arm: Convert get_phys_addr_lpae() to not return FSC values Date: Tue, 5 Dec 2017 19:46:25 +0000 Message-Id: <1512503192-2239-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> Make get_phys_addr_v6() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell --- target/arm/helper.c | 41 ++++++++++++++++++----------------------- 1 file changed, 18 insertions(+), 23 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e95e3d..a2a0784 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,7 +34,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, uint32_t *fsr, + target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); /* Security attributes for an address, as returned by v8m_security_lookup. */ @@ -8277,10 +8277,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr s2pa; int s2prot; int ret; - uint32_t fsr; ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, - &txattrs, &s2prot, &s2size, &fsr, fi, NULL); + &txattrs, &s2prot, &s2size, fi, NULL); if (ret) { fi->s2addr = addr; fi->stage2 = true; @@ -8603,15 +8602,6 @@ do_fault: return true; } -/* Fault type for long-descriptor MMU fault reporting; this corresponds - * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. - */ -typedef enum { - translation_fault = 1, - access_fault = 2, - permission_fault = 3, -} MMUFaultType; - /* * check_s2_mmu_setup * @cpu: ARMCPU @@ -8713,13 +8703,13 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, uint32_t *fsr, + target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { ARMCPU *cpu = arm_env_get_cpu(env); CPUState *cs = CPU(cpu); /* Read an LPAE long-descriptor translation table. */ - MMUFaultType fault_type = translation_fault; + ARMFaultType fault_type = ARMFault_Translation; uint32_t level; uint32_t epd = 0; int32_t t0sz, t1sz; @@ -8829,7 +8819,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, ttbr_select = 1; } else { /* in the gap between the two regions, this is a Translation fault */ - fault_type = translation_fault; + fault_type = ARMFault_Translation; goto do_fault; } @@ -8915,7 +8905,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, ok = check_s2_mmu_setup(cpu, aarch64, startlevel, inputsize, stride); if (!ok) { - fault_type = translation_fault; + fault_type = ARMFault_Translation; goto do_fault; } level = startlevel; @@ -9001,7 +8991,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, /* Here descaddr is the final physical address, and attributes * are all in attrs. */ - fault_type = access_fault; + fault_type = ARMFault_AccessFlag; if ((attrs & (1 << 8)) == 0) { /* Access flag */ goto do_fault; @@ -9019,7 +9009,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); } - fault_type = permission_fault; + fault_type = ARMFault_Permission; if (!(*prot & (1 << access_type))) { goto do_fault; } @@ -9051,8 +9041,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, return false; do_fault: - /* Long-descriptor format IFSR/DFSR value */ - *fsr = (1 << 9) | (fault_type << 2) | level; + fi->type = fault_type; + fi->level = level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); return true; @@ -9778,8 +9768,9 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, /* S1 is done. Now do S2 translation. */ ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, phys_ptr, attrs, &s2_prot, - page_size, fsr, fi, + page_size, fi, cacheattrs != NULL ? &cacheattrs2 : NULL); + *fsr = arm_fi_to_lfsc(fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ *prot &= s2_prot; @@ -9858,8 +9849,12 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, - attrs, prot, page_size, fsr, fi, cacheattrs); + bool ret = get_phys_addr_lpae(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); + + *fsr = arm_fi_to_lfsc(fi); + return ret; } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { bool ret = get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, page_size, fi);