From patchwork Thu Dec 7 18:14:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121041 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8688614qgn; Thu, 7 Dec 2017 10:14:57 -0800 (PST) X-Google-Smtp-Source: AGs4zMaynoLzp+9aNgCdM9IMuL4UkrVNEkKrAUmMUjqdeu8ymRRe83F+YuW8YPfNncCNyK/EPKQY X-Received: by 10.28.214.145 with SMTP id n139mr2054044wmg.59.1512670497100; Thu, 07 Dec 2017 10:14:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512670497; cv=none; d=google.com; s=arc-20160816; b=Q95B7SyZy8ydsyBKQ5p7Sm/CurnbbKcFV8mAS0z4csTLO3tvBOKm78ujV4IdV9o3lp 9uhHHTJAznxF1K/ZWAff+JB4zQOwL6z/DaFu7+C7Y+uwdAsLq+v5aD/wjEvmLwNvu/P1 AhhB6xbF3EEj+ToxpFQ4tqUQcMciqNTJ/w/d7rpXIsDIEl1kljc8nEbs0U4vUEm7K+RO YHWK5rFvnteWnSuAczl6KuGBuMLGRmQ3ELv82RbGkaqnNK3LBfRaG/Bx3mRUAqUjc5+n TBPqiSXGBx2wyq8rlpLsVCk0JdaY7EwmzxcsmiaINIrwacrek5lCQWmm5Wfub8A9sz1J H/oQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=gdamzciN9oYeOnQEXtDEInhoS4qKKlsZvZNP31PgOHQ=; b=TQJHcjDzoHZBO9zXiJKHS+slvmIWm/sty47kOdQc3K/mBaaViIBybVMgSHEM7QuOuk 3/p0IW3AuV+gSu6vRGdI5gI8/+62R6NwaPrHKV5PUCVQjrOqrAEaA4pQ63xGoKCF7cAx Mj848i+730x3niNafeoxdlAY17qxcumUXROLTx5wDK02ImiCbxTBGmjurhZLuvri+1+l qs4mbwmG8AsgGgrzo3spg3Rs2YwVYbA3j1Vf2VqzT/XLKwPW4PbIwXkw3lq9O4aWRwuD 1BiYQPIV5fr8MVnkcpdJu/PGz7YTxcRiTkQWKzZoKH5szHoKGvd+v9StB48tmfxWahAt 7ZdA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 103si4255711wrc.215.2017.12.07.10.14.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 10:14:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eN0hE-00081p-Ew; Thu, 07 Dec 2017 18:14:56 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Eduardo Habkost , "Richard W . M . Jones" Subject: [PATCH 3/6] target/arm: Move definition of 'host' cpu type into cpu.c Date: Thu, 7 Dec 2017 18:14:50 +0000 Message-Id: <1512670493-18114-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> References: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> Move the definition of the 'host' cpu type into cpu.c, where all the other CPU types are defined. We can do this now we've decoupled it from the KVM-specific host feature probing. This means we now create the type unconditionally (assuming we were built with KVM support at all), but if you try to use it without -enable-kvm this will end up in the "host cpu probe failed and KVM not enabled" path in arm_cpu_realizefn(), for an appropriate error message. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 24 ++++++++++++++++++++++++ target/arm/kvm.c | 19 ------------------- 2 files changed, 24 insertions(+), 19 deletions(-) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a7deb10..9304277 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1785,6 +1785,26 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #endif } +#ifdef CONFIG_KVM +static void arm_host_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + kvm_arm_set_cpu_features_from_host(cpu); +} + +static const TypeInfo host_arm_cpu_type_info = { + .name = TYPE_ARM_HOST_CPU, +#ifdef TARGET_AARCH64 + .parent = TYPE_AARCH64_CPU, +#else + .parent = TYPE_ARM_CPU, +#endif + .instance_init = arm_host_initfn, +}; + +#endif + static void cpu_register(const ARMCPUInfo *info) { TypeInfo type_info = { @@ -1822,6 +1842,10 @@ static void arm_cpu_register_types(void) cpu_register(info); info++; } + +#ifdef CONFIG_KVM + type_register_static(&host_arm_cpu_type_info); +#endif } type_init(arm_cpu_register_types) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 945696c..6bdc027 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -152,23 +152,6 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) env->features = arm_host_cpu_features.features; } -static void kvm_arm_host_cpu_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - kvm_arm_set_cpu_features_from_host(cpu); -} - -static const TypeInfo host_arm_cpu_type_info = { - .name = TYPE_ARM_HOST_CPU, -#ifdef TARGET_AARCH64 - .parent = TYPE_AARCH64_CPU, -#else - .parent = TYPE_ARM_CPU, -#endif - .instance_init = kvm_arm_host_cpu_initfn, -}; - int kvm_arch_init(MachineState *ms, KVMState *s) { /* For ARM interrupt delivery is always asynchronous, @@ -184,8 +167,6 @@ int kvm_arch_init(MachineState *ms, KVMState *s) cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); - type_register_static(&host_arm_cpu_type_info); - return 0; }