From patchwork Thu Dec 7 18:14:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121042 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8688625qgn; Thu, 7 Dec 2017 10:14:57 -0800 (PST) X-Google-Smtp-Source: AGs4zMYdDHumRWETl4N8jGk3zOZJ7jaP9rJ/ScI6GdN6zPtNsdR9GOgnP5Hb8lmW47VybI8Lgsj2 X-Received: by 10.28.150.20 with SMTP id y20mr1802371wmd.118.1512670497707; Thu, 07 Dec 2017 10:14:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512670497; cv=none; d=google.com; s=arc-20160816; b=FepojQjaDjroo0XjfPJyhAim5P01C4h+yaVZGTA1Sq4kw0wh4e0vD9vorIGrYWPu1G hgfFl3Td2QsRKA316amBuenMIiDuPyI+jxEgL4/yJsb0z8u6REABID0DngdyRrXVYXTD tJ/w3v0xffayASGJITAwXajXFOeSgfe9O9X8+0toC0qcHk+Besjf9DoIjkjjP4VB8Xxl CnY1lNoPYB4Dfn+1srz7KjAc/LS1XeEInraXcOsbjv2c819XXlQjBS0yKn51ah4lfr/+ zUUU8HuLfqBJqilGD1V9i53S1DuI90JtC7lSJ6FXXfJKbWJOyrGnDEb471GR7n+qI6TH nnMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=AycHsIRaG0/Tbl3bGwvTv1KREHsLLnG8IgJjSRf9kao=; b=CDoPRdP4i73834nJIm5uwxW/5vxWWVXBaCgt2wmewZYG3vS6hDEbI5yOnBTNfb84h6 /ZALYqxGlhUtxwBzx4D4dd4MptbEBMwOHgrdIYN1FoJNiS3AfiEBHD6W6IvgeafNWY2H J7nbe4sSkWU+jP9XynYv5CzwfO+vVMuCVwriJeCP5bjCPPq/FEXhWf/QoDx1KFvHKOdN ZyOWTXF8MF2T/j68dVsq/CdpNLZdjld5UfIYyiHHNUVhSk9tU4tnXjf9L7LANhDiur4X qxEE39j3vYydnFWtAdB+ScgDjg/U2StQxfA/c3FGpFyQac2AhV0VbGzubdKS9XviL9wp sJXw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id l25si4322848wra.368.2017.12.07.10.14.57 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 10:14:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eN0hF-000825-4U; Thu, 07 Dec 2017 18:14:57 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Eduardo Habkost , "Richard W . M . Jones" Subject: [PATCH 4/6] target/arm: Add "-cpu max" support Date: Thu, 7 Dec 2017 18:14:51 +0000 Message-Id: <1512670493-18114-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> References: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> Add support for "-cpu max" for ARM guests. This CPU type behaves like "-cpu host" when KVM is enabled, and like a system CPU with the maximum possible feature set otherwise. (Note that this means it won't be migratable across versions, as we will likely add features to it in future.) Signed-off-by: Peter Maydell --- target/arm/cpu-qom.h | 2 ++ target/arm/cpu.c | 24 ++++++++++++++++++++++++ target/arm/cpu64.c | 21 +++++++++++++++++++++ 3 files changed, 47 insertions(+) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index a42495b..d135ff8 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -33,6 +33,8 @@ struct arm_boot_info; #define ARM_CPU_GET_CLASS(obj) \ OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) +#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU + /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9304277..190da97 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1628,6 +1628,27 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr = 0x00000078; } +#ifndef TARGET_AARCH64 +/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); + * otherwise, a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; + * this only needs to handle 32 bits. + */ +static void arm_max_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (kvm_enabled()) { + kvm_arm_set_cpu_features_from_host(cpu); + } else { + cortex_a15_initfn(obj); + /* In future we might add feature bits here even if the + * real-world A15 doesn't implement them. + */ + } +} +#endif + #ifdef CONFIG_USER_ONLY static void arm_any_initfn(Object *obj) { @@ -1691,6 +1712,9 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, +#ifndef TARGET_AARCH64 + { .name = "max", .initfn = arm_max_initfn }, +#endif #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = arm_any_initfn }, #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07a..38dcf32 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -28,6 +28,7 @@ #include "hw/arm/arm.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" +#include "kvm_arm.h" static inline void set_feature(CPUARMState *env, int feature) { @@ -212,6 +213,25 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } +/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); + * otherwise, a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; + * this only needs to handle 64 bits. + */ +static void aarch64_max_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (kvm_enabled()) { + kvm_arm_set_cpu_features_from_host(cpu); + } else { + aarch64_a57_initfn(obj); + /* In future we might add feature bits here even if the + * real-world A57 doesn't implement them. + */ + } +} + #ifdef CONFIG_USER_ONLY static void aarch64_any_initfn(Object *obj) { @@ -240,6 +260,7 @@ typedef struct ARMCPUInfo { static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, + { .name = "max", .initfn = aarch64_max_initfn }, #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = aarch64_any_initfn }, #endif