From patchwork Wed Dec 13 16:52:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121797 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5709799qgn; Wed, 13 Dec 2017 08:52:25 -0800 (PST) X-Google-Smtp-Source: ACJfBosHIfeqpQyjLW2AxvFdRga2z2ytk9cOrWEtdig5Guimd/YACOOOZ7mbBbLQJMJc2afJCcJN X-Received: by 10.28.137.5 with SMTP id l5mr2691746wmd.123.1513183945223; Wed, 13 Dec 2017 08:52:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513183945; cv=none; d=google.com; s=arc-20160816; b=mukcU+cjCj3BMXDPC2cMQef8cMgOAjMRO7y2ohG32G4idY1rUc0jOo+n+fc+nag4Lt IBo6ho414EKwpw+a6ID+C9gsFm3+mMCBcRiRH3lFu8xQyBomPAqKJpfqhYQcjZa5SEfe V1HfamkUaYZqAyJObFhMy8Q6lkLW4VTmkwwTO+vFIefK14mtWHMIh+X4ub/+I08WZ9Rv nnEOGfiYPAHgwV3XUHoIl9cGoreCFgaUH00Gi/cu0Cbjadj7HRFpvF/sNO+SU1TUN5mz GKrzijbnGXpreTUk6wripGay5s3fLjZDzi+gYJMLB0tzlOr/9l3kqKDqfd/xFS5eZHPX iGrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=gUU4tqNCfsNprvJRsRytJfnLhN2Y+PYyU4SMpLbCNEU=; b=zRJ0dECmUJZagYH7M9NgnAu32I44ikCJsRxnesllNhO+D4QOq3lLoAOVTQZBercl63 E1bk2tgMY2F1qHKKDvZrBAai+i2bJvHg0JUNYbcVwjSxZLhSgRV9Tb3MxxTKEr44Qo8w yAJM6guRhvJOYQqAcIA29/r6ZkGdTyA6JbFSfAfdcvlEpj6yX6mkxZIWrT0MU644eMZ6 nSORvUvaHRm93TguI1VUNLXeiCEU9l3OGCE7lSv6LouqHuJpp3nvlTJ2oT5LkJSYWhl0 cXgv9q/ZZLDKj0F0hkNO1xdSqiaZV8BcDIMwseww0ST0Qn09lSIqk3mY3QQ8hcE8zegM bSNw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id n68si1688240wmg.151.2017.12.13.08.52.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Dec 2017 08:52:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ePAGe-0007Oi-Ec; Wed, 13 Dec 2017 16:52:24 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Laszlo Ersek , Ard Biesheuvel Subject: [PATCH 2/2] hw/intc/arm_gic: reserved register addresses are RAZ/WI Date: Wed, 13 Dec 2017 16:52:21 +0000 Message-Id: <1513183941-24300-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513183941-24300-1-git-send-email-peter.maydell@linaro.org> References: <1513183941-24300-1-git-send-email-peter.maydell@linaro.org> The GICv2 specification says that reserved register addresses must RAZ/WI; now that we implement external abort handling for Arm CPUs this means we must return MEMTX_OK rather than MEMTX_ERROR, to avoid generating a spurious guest data abort. Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Alistair Francis diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 5a0e2a3..d701e49 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1261,7 +1261,8 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_read: Bad offset %x\n", (int)offset); - return MEMTX_ERROR; + *data = 0; + break; } return MEMTX_OK; } @@ -1329,7 +1330,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_write: Bad offset %x\n", (int)offset); - return MEMTX_ERROR; + return MEMTX_OK; } gic_update(s); return MEMTX_OK;