From patchwork Wed Dec 13 17:52:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121801 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5779230qgn; Wed, 13 Dec 2017 09:52:39 -0800 (PST) X-Google-Smtp-Source: ACJfBotatjJnBq3TW/WpCLI8g27T8oyJdNnACgvmhuYMYrNyGlg8IZs9hcMKDYI/oFBjxwSN9Itu X-Received: by 10.101.90.138 with SMTP id c10mr5955150pgt.441.1513187559462; Wed, 13 Dec 2017 09:52:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513187559; cv=none; d=google.com; s=arc-20160816; b=xiK+HFo1zVSbPCJpvJU2QQ1rU6KtCVYUUPCPamUvhwp1BkNJVdpmU/9vosc8b68D4f hmzUx5emdDJM4d8XzW2VjEA1mwF3dINmIyt+o3zpxHWq1IkPqtR66Q+YXMN8hVJf5GpI qL1IeFQor+Uvg9Hu8MkI7UPTJKVWt7JIl6GHi0VtDpKOw1RaefzRkN0VPmFSOGMZyHi3 Q70JWiNZFZ6NTuMnCIAywlcrHr2Ree10s3WPP6DL+MXhgYDHDUOXejRaAnr0A+WM1xDf ze3pyimJoJ/daHbeJnw8wqzGtyYZlaequ0XvrBKAyf6NGhPTMi8ipPMa33mS+djdpVsK X/Ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=/sdnIQJa4p1fTvFWMoBoWF4vhTfrKggMgvJP/XaH9ZY=; b=lHBBJxIKCmWfNY3e2ktCTEf+eZ17e6fMgA7a0yikTuoYv8vYzvPQ3Yhok0a9I0kQTZ G/3mIYGAZTSYvUSb7oEZq4pBqcIefh70mqDu+KbVC1b8ei7teImDjzouewP9jyJH1+8y q5NrdTILC9SNyGaQvzY68RetWbLo/4rmWATgD+eFa9vO1Q8KbY8IMXGZQSq4paLkKvWf XgJm52SdnzV2WnDDHwJywL0Fb0IPFtuEPduXcAArsx5m/rMpsk4bC7yDAqAgrfzfqfxf CL1KK2S5cLe4XdoLX8MVPU41su2YXJdx2zujejwc9/YPGnfsgfUu/1RIi/RgWZFi0V/z gblg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id bf4si1736404plb.142.2017.12.13.09.52.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Dec 2017 09:52:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ePBCp-0007VA-Sa; Wed, 13 Dec 2017 17:52:31 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Aurelien Jarno , Yongbok Kim , Paul Burton Subject: [PATCH 1/2] exec: Don't reuse unassigned_mem_ops for io_mem_rom Date: Wed, 13 Dec 2017 17:52:28 +0000 Message-Id: <1513187549-2435-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513187549-2435-1-git-send-email-peter.maydell@linaro.org> References: <1513187549-2435-1-git-send-email-peter.maydell@linaro.org> We set up the io_mem_rom special memory region using the unassigned_mem_ops structure; this is then used when a guest tries to write to ROM. This is incorrect, because the behaviour of unassigned memory may be different from that of ROM for writes. In particular, on some architectures writing to unassigned memory generates a guest exception, whereas writing to ROM is generally ignored. Use a special readonly_mem_ops for this purpose instead, so writes to ROM are ignored for all guest CPUs. Signed-off-by: Peter Maydell --- exec.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/exec.c b/exec.c index 03238a3..74b8727 100644 --- a/exec.c +++ b/exec.c @@ -2720,6 +2720,37 @@ static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) return phys_section_add(map, §ion); } +static void readonly_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + /* Ignore any write to ROM. */ +} + +static bool readonly_mem_accepts(void *opaque, hwaddr addr, + unsigned size, bool is_write) +{ + return is_write; +} + +/* This will only be used for writes, because reads are special cased + * to directly access the underlying host ram. + */ +static const MemoryRegionOps readonly_mem_ops = { + .write = readonly_mem_write, + .valid.accepts = readonly_mem_accepts, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 8, + .unaligned = false, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 8, + .unaligned = false, + }, +}; + MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs) { int asidx = cpu_asidx_from_attrs(cpu, attrs); @@ -2732,7 +2763,8 @@ MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs) static void io_mem_init(void) { - memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); + memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops, + NULL, NULL, UINT64_MAX); memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);