From patchwork Sun Jun 23 17:04:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 167533 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3231858ilk; Sun, 23 Jun 2019 10:14:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqx79R8Xh7/saH9fqFMSEF8oaJY/H9SCupZBxD00OGgC4OtzpojV1P97ANs6nN9tQYIuWKMb X-Received: by 2002:a17:906:a394:: with SMTP id k20mr105114148ejz.46.1561310065662; Sun, 23 Jun 2019 10:14:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561310065; cv=none; d=google.com; s=arc-20160816; b=SJckrEn8cnxbUZtkQS/0HPBkbq+yFLXy7wtF2bA9LKPlDdEJQ6ZlfIbJKfYvV3lh5d 8YB/bJQdZub0l+H8sRTrMbqpqj1TflDQkJ997xu0v8ppNl4qjre14wQU/SsHNtHuI+k2 A3Dt0TVE9FZRyqteAj9+MG+oDSG0kIe2dU1bZLa/9nU8hEMTbbQ1DKQu8uB8A0Elou33 xnArxVzDspG2JfKEj4M9op1omuBg7JBPVcJZ86g6HIcUauorPBthbZ2oA38o9G97y6o4 g11Wj6D5hEqMMrCwGMfiWX9uFACWKnlh852aGCpiK1XGfbt49i+AoBdK0InSPidJvpyC k7Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from; bh=htkHTQbYIB06oT1HPZB53EDZOs75FT6kMfZg8Y8e7+0=; b=VoM1mca9MegXhEpyx0ylshpM0lKHQUrswSatT/lboHWQF8LXzUdkiUf5Cqt3l28gt0 aLD6KABRUPdYWDWXjjSxbR4TwvS+6wstufBawpfguR7WTKMfHYPPG4p5QxWXvJGfHirA VA05cORPHc3Omtm80WhEJYwbevJkDquAAEoMFRe2KeAzP+W5g876GqiKxbuGoT3wZcfg PZCJZhqTn5J0gDROqR63SeGKNhSzMCCFFlo5NDKtYJm7geb4vKz0f/qxPM/YHlxmHRPT k5KtR/fdzQ2DjX6XlhGgNOLn3CHaRIjDzNHss5RkGk1YCW1ftVCQLGoVA0OlCjVGqDFc r7Rg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z40si7427701edc.260.2019.06.23.10.14.25 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Jun 2019 10:14:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:45838 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf64O-0000fH-K7 for patch@linaro.org; Sun, 23 Jun 2019 13:14:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34153) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf5wM-0001d1-Mh for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hf5wL-0004IZ-D8 for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:06 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41126 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hf5wL-0004HA-5M for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:05 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6421A1A1D78; Sun, 23 Jun 2019 19:05:45 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3FACD1A1D85; Sun, 23 Jun 2019 19:05:45 +0200 (CEST) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sun, 23 Jun 2019 19:04:40 +0200 Message-Id: <1561309489-16146-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 07/16] tcg/ppc: Add support for vector add/subtract X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, "David Gibson --cc=amarkovic @ wavecomp . com" , Mark Cave-Ayland , Aleksandar Markovic , hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Add support for vector add/subtract using Altivec instructions: VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.inc.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.7.4 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index e1142e7..e254fa4 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -474,6 +474,14 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define STVX XO31(231) #define STVEWX XO31(199) +#define VADDUBM VX4(0) +#define VADDUHM VX4(64) +#define VADDUWM VX4(128) + +#define VSUBUBM VX4(1024) +#define VSUBUHM VX4(1088) +#define VSUBUWM VX4(1152) + #define VMAXSB VX4(258) #define VMAXSH VX4(322) #define VMAXSW VX4(386) @@ -2831,6 +2839,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_andc_vec: case INDEX_op_not_vec: return 1; + case INDEX_op_add_vec: + case INDEX_op_sub_vec: case INDEX_op_smax_vec: case INDEX_op_smin_vec: case INDEX_op_umax_vec: @@ -2932,6 +2942,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { static const uint32_t + add_op[4] = { VADDUBM, VADDUHM, VADDUWM, 0 }, + sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, 0 }, eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 }, gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 }, gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }, @@ -2955,6 +2967,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_dupm_vec(s, type, vece, a0, a1, a2); return; + case INDEX_op_add_vec: + insn = add_op[vece]; + break; + case INDEX_op_sub_vec: + insn = sub_op[vece]; + break; case INDEX_op_smin_vec: insn = smin_op[vece]; break; @@ -3253,6 +3271,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return (TCG_TARGET_REG_BITS == 64 ? &S_S : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S); + case INDEX_op_add_vec: + case INDEX_op_sub_vec: case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: