diff mbox series

[v3,10/11] target/arm/helper: make it clear the EC field is also in hex

Message ID 20170307155054.5833-11-alex.bennee@linaro.org
State Superseded
Headers show
Series MTTCG fix-ups for 2.9 | expand

Commit Message

Alex Bennée March 7, 2017, 3:50 p.m. UTC 
..just like the rest of the displayed ESR register. Otherwise people
might scratch their heads if a not obviously hex number is displayed
for the EC field.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: KONRAD Frederic <fred.konrad@greensocs.com>

---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.11.0

Comments

Philippe Mathieu-Daudé March 7, 2017, 5:49 p.m. UTC | #1 
On 03/07/2017 12:50 PM, Alex Bennée wrote:
> ..just like the rest of the displayed ESR register. Otherwise people

> might scratch their heads if a not obviously hex number is displayed

> for the EC field.

>

> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

> Reviewed-by: KONRAD Frederic <fred.konrad@greensocs.com>


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


> ---

>  target/arm/helper.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

>

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index 3f4211b572..76b608f0ba 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -6857,7 +6857,7 @@ void arm_cpu_do_interrupt(CPUState *cs)

>                    new_el);

>      if (qemu_loglevel_mask(CPU_LOG_INT)

>          && !excp_is_internal(cs->exception_index)) {

> -        qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",

> +        qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",

>                        env->exception.syndrome >> ARM_EL_EC_SHIFT,

>                        env->exception.syndrome);

>      }

>
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3f4211b572..76b608f0ba 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6857,7 +6857,7 @@  void arm_cpu_do_interrupt(CPUState *cs)
                   new_el);
     if (qemu_loglevel_mask(CPU_LOG_INT)
         && !excp_is_internal(cs->exception_index)) {
-        qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
+        qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",
                       env->exception.syndrome >> ARM_EL_EC_SHIFT,
                       env->exception.syndrome);
     }