From patchwork Tue Aug 15 14:57:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 110171 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp5774563qge; Tue, 15 Aug 2017 07:57:50 -0700 (PDT) X-Received: by 10.200.26.68 with SMTP id q4mr36567790qtk.295.1502809070847; Tue, 15 Aug 2017 07:57:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502809070; cv=none; d=google.com; s=arc-20160816; b=VscBJ2vSGt0Jj92eZH3nganZ4au6xjLavfPdG2s7dLxAE0WofcKNsdpeSe1uCnTmtc XJzbKybVnI9Dc5yL0sPJbH1bOWW3m3IFdFtV9y74j7eFKRWwGTZElMeTuc+l0SLGqfQZ +pI3wR4uhZ0dLjZznt7xqNf925rqvioiiW4H3p8zS8WGdLUxnIOKthSGsLQSl8r5r7qF a6Svlnc2DYbdPZGtLvDCLjCBJrf0efmVaWOAuVh7mQB4RSGKTnmenxkPIrj3h5i16BJ+ gk+vApcs6Tp8ZKPJkNTA9165e04wJgZZ7em+OvBJZC7b8mGt/a2Scfa4PxhPGXPrMmws oEzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=aKSHdHsWCeTS98zZ+zVKyMBhPWkI6YZN9ENm/xYAoRs=; b=FvI1ryNkUZ718owL+ZNaieEr+BSPFOCAh7xH7B6OdBMo00dSKPQN2xy++HquB2x5oA Q1sNTlr8XCo0IZ2vOL6GmpJK2ivyJwEo7kVjhWvwKx+Fa/asZIhRzckzDr2E5YErT/bt QGNzr52CfVi1o1aj1wQuhj0OfJrxsiILLFM0GfICU7rZHbudIbKxYoUyTP9XGHRZC+QE 93KreyviR7VLKccQ4NnIIXrMQbVl09dUi+IUQ9ke3OCJC0fna96QyYQzmvAZxuOnwLDY 3oluLeSp7CM2CjISdRxkAlKunXTms4BVQ8CuWxfxK7ZjCopx6f137ToiptgRMtEAar1F RMrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VTsDvDUo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q131si8744354qka.15.2017.08.15.07.57.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 15 Aug 2017 07:57:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VTsDvDUo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39158 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhdHw-0005N6-I0 for patch@linaro.org; Tue, 15 Aug 2017 10:57:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhdHX-0005Ip-TF for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:57:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dhdHV-0004J1-84 for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:57:23 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:33136) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dhdHV-0004IL-06 for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:57:21 -0400 Received: by mail-pg0-x22d.google.com with SMTP id u5so7130791pgn.0 for ; Tue, 15 Aug 2017 07:57:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aKSHdHsWCeTS98zZ+zVKyMBhPWkI6YZN9ENm/xYAoRs=; b=VTsDvDUo+NY93nq/DIadQbJnH9szLCJnAuq+OmmPkd1nbSJbzoyoPZtg29HCQXhZG0 6igN30Lv70wyXKGlI84UyPQSQ9Vcpg5woKOjUgCdN53kBgB/EkDZ9PYnOMhvWDKfzMm+ tvUQXaNZm394aGllsD0GtprO23CCdbQeDmmpQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aKSHdHsWCeTS98zZ+zVKyMBhPWkI6YZN9ENm/xYAoRs=; b=mTpm1x0uyIw6ixBMDIRtouNTM+hMXgGbA4mZhJiJjwncfd8t4q32ipTkDH44VFWuRH k5TevQ/rOZZ/NUOFRU4E5zY8i3LV1sVdLaFgE2q5KLVidM4sh926cxXdAL8hloFj6qiN VyGs1TFBFHW3e8W0fLZF4HzkRno025ELRrtuQgfivJ05IdWV9rn79Uc6/XIaBCMM9knk /ZubHB3i2B99GgGNqrQTmDQzU5+N1uWkQnrRl9X/cX4mTTfM1JuBwBxBTXsNZfCpNEyt Sb94lAIkG5/HmOdAxhgXYauUICDpUwAmZUq1HT4sZN8q03o0R4QksTTtLALh30I7aXLT wnzg== X-Gm-Message-State: AHYfb5jmPkO+faN2QxPQNFf/PBYntOlL/eiL4p4xsZ2TbzMxyWihBB6s 6jVpHIDIiefh598iXE9Mqw== X-Received: by 10.84.194.129 with SMTP id h1mr31529268pld.237.1502809039570; Tue, 15 Aug 2017 07:57:19 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id n11sm20626318pfg.15.2017.08.15.07.57.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 Aug 2017 07:57:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 Aug 2017 07:57:13 -0700 Message-Id: <20170815145714.17635-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.4 In-Reply-To: <20170815145714.17635-1-richard.henderson@linaro.org> References: <20170815145714.17635-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PATCH v2 for-2.10 2/3] target/arm: Correct load exclusive pair atomicity X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We are not providing the required single-copy atomic semantics for the 64-bit operation that is the 32-bit paired load. At the same time, leave the entire 64-bit value in cpu_exclusive_val and stop writing to cpu_exclusive_high. This means that we do not have to re-assemble the 64-bit quantity when it comes time to store. At the same time, drop a redundant temporary and perform all loads directly into the cpu_exclusive_* globals. Tested-by: Alistair Francis Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 60 ++++++++++++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 23 deletions(-) -- 2.13.4 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 113e2e172b..eac545e4f2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1853,29 +1853,42 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i64 addr, int size, bool is_pair) { - TCGv_i64 tmp = tcg_temp_new_i64(); - TCGMemOp memop = s->be_data + size; + int idx = get_mem_index(s); + TCGMemOp memop = s->be_data; g_assert(size <= 3); - tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); - if (is_pair) { - TCGv_i64 addr2 = tcg_temp_new_i64(); - TCGv_i64 hitmp = tcg_temp_new_i64(); - g_assert(size >= 2); - tcg_gen_addi_i64(addr2, addr, 1 << size); - tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); - tcg_temp_free_i64(addr2); - tcg_gen_mov_i64(cpu_exclusive_high, hitmp); - tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); - tcg_temp_free_i64(hitmp); - } + if (size == 2) { + /* The pair must be single-copy atomic for the doubleword. */ + memop |= MO_64; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + if (s->be_data == MO_LE) { + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32); + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); + } else { + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32); + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); + } + } else { + /* The pair must be single-copy atomic for *each* doubleword, + but not the entire quadword. */ + memop |= MO_64; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); - tcg_gen_mov_i64(cpu_exclusive_val, tmp); - tcg_gen_mov_i64(cpu_reg(s, rt), tmp); + TCGv_i64 addr2 = tcg_temp_new_i64(); + tcg_gen_addi_i64(addr2, addr, 8); + tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); + tcg_temp_free_i64(addr2); - tcg_temp_free_i64(tmp); + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); + tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); + } + } else { + memop |= size; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); + } tcg_gen_mov_i64(cpu_exclusive_addr, addr); } @@ -1908,14 +1921,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, tmp = tcg_temp_new_i64(); if (is_pair) { if (size == 2) { - TCGv_i64 val = tcg_temp_new_i64(); - tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); - tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); - tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, + if (s->be_data == MO_LE) { + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); + } else { + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); + } + tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); - tcg_temp_free_i64(val); + tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else if (s->be_data == MO_LE) { gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt), cpu_reg(s, rt2));