From patchwork Fri Nov 3 08:40:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 117860 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3187854qgn; Fri, 3 Nov 2017 01:43:20 -0700 (PDT) X-Google-Smtp-Source: ABhQp+T4o4DjDR6gyivDrA6YRgl/o9tG5RgN0JX+4jdA804fcgicL+yKHx0aamEIugsvTAyR7eZy X-Received: by 10.37.215.147 with SMTP id o141mr4114941ybg.484.1509698600890; Fri, 03 Nov 2017 01:43:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509698600; cv=none; d=google.com; s=arc-20160816; b=UAvHeVsjRZy/1OkPh12UEidSDcDX3PUzIAVZEaXU2AsG5GrU/honxIzFGOZ7SiCNbz 4ZTtBylBGfg5o4A4Wje+Ehy3WuycqeBd/2l3nO72d5a5gBx8rVl2k5+Ekj3zPeSIpAu7 F5LIPc/0XZNLTDubjPMtWxC5ONc6mwROHVOUEP+9VC/lhKJRCZgS0VSvknezY4CFQ50/ QtnMclUO4yfAPdl+SZVe2cc8vFFEenJFlnOMwSYNJ9LSNd7hvZM0oCBW3m+NHTdfokex r3bI0tuTC1906DR1ky+JZF1mGv+fM0gpzvbEmNiRGID6CqM/VE5eOxEdTUyTQBhAVYSc P2Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=qAKXbHRfKP2ype58aUcRZOMoKb9bP3iiBfoCjREvatw=; b=02MPu7VQ+iQ5yypjxcDO3ziDc/1xcN6r24keM47L50893z8GT2dGX8PGVr6r0tmM+A ofgEHMTpg+KroXBSQZoUCS6fajSyeGlYdyqBR0T8hDan6mSMON5/wVCyjHP/t9pQ/D48 VefKdQnLaWnTBHBbftgnGFfVIWX9906olYaXulL9lR6g8D9TZREqS00vz6Kmvlg4mHqX P5J//l6Pz8ScnoaM8hEzGyBM6ks6muvYwDHEFkstydse6zjQAH5BLk3urxleytgoi9SB VsFyOhcSiGw6GxpcDVFtJVwe+QtRw8dVP3oqc3W2/jsGcHxDMDRfkbGVtb4q5KDWjUe1 XWUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YR3uV3sg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id w5si1327071ywd.120.2017.11.03.01.43.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 03 Nov 2017 01:43:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YR3uV3sg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35418 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eAXZP-00034Y-So for patch@linaro.org; Fri, 03 Nov 2017 04:43:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48442) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eAXX6-00029v-QQ for qemu-devel@nongnu.org; Fri, 03 Nov 2017 04:40:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eAXX5-0002TU-Lm for qemu-devel@nongnu.org; Fri, 03 Nov 2017 04:40:56 -0400 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:53477) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eAXX5-0002SC-FN for qemu-devel@nongnu.org; Fri, 03 Nov 2017 04:40:55 -0400 Received: by mail-wr0-x243.google.com with SMTP id u40so1800660wrf.10 for ; Fri, 03 Nov 2017 01:40:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qAKXbHRfKP2ype58aUcRZOMoKb9bP3iiBfoCjREvatw=; b=YR3uV3sgv8wWZigdiEaARhG0JvRoBdj875BCyEkqVZGKgl3yw8GTnDaF6VyFepTkOa uhByUbBn53NW9aS61ZWKxCQ3QwPim+uQ1saoRemmQi1QgTeFVFt2nKImoUyYPSw825/H 4qCouoQpyd0mSc4ftY+SYiiD+FoWoqk6s5Fso= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qAKXbHRfKP2ype58aUcRZOMoKb9bP3iiBfoCjREvatw=; b=nBp3Jd6JlkUwsDnoYls3qYiYODJH9x+8Gt/d7xk8TS6Xz5tncDCWWWHFqxVe3R3OyB ds5qJi0x9InCJiuoN+cE2h+5quIel6PBRoc0PZg2IboVG01n5Dt6Hb15Y0tYxbtE9Bca 05JZ2MVY89Q5c+mRTmDvElde709Pu2fgEg5HVx56AgXVNabmSwZQyPjfYazI0lpEBvPe nV+JNV9Cthl8olKWutlowdm6kB4E0XCRuxqjY/TxYl4k+tXND7eFniSBeakRo1/0F2IH fNc22qkOxkE+1yiwQMwulz388B6n9515EKufbasp2b6F+yTNEbyWx5zWA9MZF13Ctn6V pRtQ== X-Gm-Message-State: AMCzsaXClgL6YMM4dnBSSYzR8N5jOTnJHnhe+G6Hv8r8ZhuQIWIjyizB N+MEc5GJ4ml1Ro1M0dF4tjxXGwJMU8s= X-Received: by 10.223.150.76 with SMTP id c12mr5468325wra.10.1509698454132; Fri, 03 Nov 2017 01:40:54 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (p57A4515F.dip0.t-ipconnect.de. [87.164.81.95]) by smtp.gmail.com with ESMTPSA id e6sm12548347wrg.53.2017.11.03.01.40.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Nov 2017 01:40:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 Nov 2017 09:40:46 +0100 Message-Id: <20171103084046.12821-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171103084046.12821-1-richard.henderson@linaro.org> References: <20171103084046.12821-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PULL 3/3] cpu-exec: Exit exclusive region on longjmp from step_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Commit ac03ee5331612e44be narrowed the scope of the exclusive region so it only covers when we're executing the TB, not when we're generating it. However it missed that there is more than one execution path out of cpu_tb_exec -- if the atomic insn causes an exception then the code will longjmp out, skipping the code to end the exclusive region. This causes QEMU to hang the next time the CPU calls start_exclusive(), waiting for itself to exit the region. Move the "end the region" code out to the end of the function so that it is run for both normal exit and also for exit-via-longjmp. We have to use a volatile bool flag to decide whether we need to end the region, because we can longjump out of the codegen as well as the execution. (For some reason this only reproduces for me with a clang optimized build, not a gcc debug build.) Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Fixes: ac03ee5331612e44beb393df2b578c951d27dc0d Signed-off-by: Peter Maydell Message-Id: <1509640536-32160-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) -- 2.13.6 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4318441e4c..61297f8f4a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -233,6 +233,8 @@ void cpu_exec_step_atomic(CPUState *cpu) uint32_t flags; uint32_t cflags = 1; uint32_t cf_mask = cflags & CF_HASH_MASK; + /* volatile because we modify it between setjmp and longjmp */ + volatile bool in_exclusive_region = false; if (sigsetjmp(cpu->jmp_env, 0) == 0) { tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); @@ -251,14 +253,12 @@ void cpu_exec_step_atomic(CPUState *cpu) /* Since we got here, we know that parallel_cpus must be true. */ parallel_cpus = false; + in_exclusive_region = true; cc->cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); cc->cpu_exec_exit(cpu); - parallel_cpus = true; - - end_exclusive(); } else { /* We may have exited due to another problem here, so we need * to reset any tb_locks we may have taken but didn't release. @@ -270,6 +270,15 @@ void cpu_exec_step_atomic(CPUState *cpu) #endif tb_lock_reset(); } + + if (in_exclusive_region) { + /* We might longjump out of either the codegen or the + * execution, so must make sure we only end the exclusive + * region if we started it. + */ + parallel_cpus = true; + end_exclusive(); + } } struct tb_desc {