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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id h69sm26553411pfe.107.2017.12.18.09.30.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:30:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:30:22 -0800 Message-Id: <20171218173022.18418-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218173022.18418-1-richard.henderson@linaro.org> References: <20171218173022.18418-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 9/9] target/arm: Add ARM_FEATURE_SVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Enable it for the "any" CPU used by aarch64-linux-user. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) -- 2.14.3 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 37b8cef2e2..652e00d957 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1386,6 +1386,7 @@ enum arm_features { ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ + ARM_FEATURE_SVE, /* has SVE extension */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 43b42f95fd..366ab2eeee 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -229,6 +229,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + set_feature(&cpu->env, ARM_FEATURE_SVE); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ }