[37/38] target/hppa: Increase number of temp regs

Message ID	20171229063145.29167-38-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Thu, 28 Dec 2017 22:31:44 -0800 Message-Id: <20171229063145.29167-38-richard.henderson@linaro.org> In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org> References: <20171229063145.29167-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH 37/38] target/hppa: Increase number of temp regs Precedence: list Cc: deller@gmx.de Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	Add hppa-softmmu \| expand [00/38] Add hppa-softmmu [01/38] target/hppa: Skeleton support for hppa-softmmu [02/38] target/hppa: Define the rest of the PSW [03/38] target/hppa: Disable gateway page emulation for system mode [04/38] target/hppa: Define hardware exception types [05/38] target/hppa: Split address size from register size [06/38] target/hppa: Implement mmu_idx from IA privilege level [07/38] target/hppa: Implement the system mask instructions [08/38] target/hppa: Add space registers [09/38] target/hppa: Add control registers [10/38] target/hppa: Adjust insn mask for mfctl, w [11/38] target/hppa: Implement rfi [12/38] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt [13/38] target/hppa: Implement unaligned access trap [14/38] target/hppa: Use space registers in data operations [15/38] target/hppa: Do not set cs_base to iaoq_b [16/38] target/hppa: Avoid privilege level decrease during branches [17/38] target/hppa: Implement IASQ [18/38] target/hppa: Implement tlb_fill [19/38] target/hppa: Implement external interrupts [20/38] target/hppa: Implement the interval timer [21/38] target/hppa: Log unimplemented instructions [22/38] target/hppa: Implement ITLBA and ITLBP insns [23/38] target/hppa: Implement PTLB and PTLBE insns [24/38] target/hppa: Implement LDWA [25/38] target/hppa: Implement LPA [26/38] target/hppa: Implement LCI [27/38] target/hppa: Implement SYNCDMA insn [28/38] target/hppa: Implement a halt instruction [29/38] hw/hppa: Implement DINO system board [30/38] target/hppa: Optimize for flat addressing space [31/38] target/hppa: Add system registers to gdbstub [32/38] target/hppa: Add migration for the cpu [33/38] target/hppa: Implement B,GATE insn [34/38] target/hppa: Only use EXCP_DTLB_MISS [35/38] qom: Add MMU_DEBUG_LOAD [36/38] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] [37/38] target/hppa: Increase number of temp regs [38/38] target/hppa: Fix comment

Message ID

20171229063145.29167-38-richard.henderson@linaro.org

State

Superseded

Headers

Received-SPF: pass (google.com: domain of
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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Thu, 28 Dec 2017 22:31:44 -0800
Message-Id: <20171229063145.29167-38-richard.henderson@linaro.org>
In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org>
References: <20171229063145.29167-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH 37/38] target/hppa: Increase number of temp regs
Precedence: list
Cc: deller@gmx.de
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

Add hppa-softmmu | expand

Commit Message

Richard Henderson Dec. 29, 2017, 6:31 a.m. UTC

HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot,
which uses at least 5 temps.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/hppa/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.14.3

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4430a4bfdb..680a361d29 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -273,7 +273,7 @@  typedef struct DisasContext {
     TCGv_reg iaoq_n_var;
 
     int ntempr, ntempl;
-    TCGv_reg tempr[4];
+    TCGv_reg tempr[8];
     TCGv_tl  templ[4];
 
     DisasCond null_cond;

[37/38] target/hppa: Increase number of temp regs

Commit Message

Patch