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[24.181.135.57]) by smtp.gmail.com with ESMTPSA id c83sm1281024pfk.8.2018.01.15.19.34.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Jan 2018 19:34:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 15 Jan 2018 19:33:49 -0800 Message-Id: <20180116033404.31532-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180116033404.31532-1-richard.henderson@linaro.org> References: <20180116033404.31532-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v9 11/26] tcg: Loosen vec_gen_op* typecheck rules X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For ARM SVE with VQ=3, we want to be able to dup a scalar into a v256, use that, and then perform a second operation with the v256 punned to a v128. Allow operands to a vector operation be wider than necessary for the output. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) -- 2.14.3 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index a73d094ddb..ad9a45b653 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -78,7 +78,7 @@ static void vec_gen_op2(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a) TCGTemp *at = tcgv_vec_temp(a); TCGType type = rt->base_type; - tcg_debug_assert(at->base_type == type); + tcg_debug_assert(at->base_type >= type); vec_gen_2(opc, type, vece, temp_arg(rt), temp_arg(at)); } @@ -90,8 +90,8 @@ static void vec_gen_op3(TCGOpcode opc, unsigned vece, TCGTemp *bt = tcgv_vec_temp(b); TCGType type = rt->base_type; - tcg_debug_assert(at->base_type == type); - tcg_debug_assert(bt->base_type == type); + tcg_debug_assert(at->base_type >= type); + tcg_debug_assert(bt->base_type >= type); vec_gen_3(opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt)); } @@ -257,14 +257,14 @@ void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a) if (TCG_TARGET_REG_BITS == 64) { TCGArg ai = tcgv_i64_arg(a); - vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai); + vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } else if (vece == MO_64) { TCGArg al = tcgv_i32_arg(TCGV_LOW(a)); TCGArg ah = tcgv_i32_arg(TCGV_HIGH(a)); vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah); } else { TCGArg ai = tcgv_i32_arg(TCGV_LOW(a)); - vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai); + vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } } @@ -493,8 +493,8 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGType type = rt->base_type; int can; - tcg_debug_assert(at->base_type == type); - tcg_debug_assert(bt->base_type == type); + tcg_debug_assert(at->base_type >= type); + tcg_debug_assert(bt->base_type >= type); can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece); if (can > 0) { vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); @@ -515,8 +515,8 @@ void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) TCGType type = rt->base_type; int can; - tcg_debug_assert(at->base_type == type); - tcg_debug_assert(bt->base_type == type); + tcg_debug_assert(at->base_type >= type); + tcg_debug_assert(bt->base_type >= type); can = tcg_can_emit_vec_op(INDEX_op_mul_vec, type, vece); if (can > 0) { vec_gen_3(INDEX_op_mul_vec, type, vece, ri, ai, bi);