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[PULL,37/43] target/hppa: Implement LDSID for system mode

Message ID	20180122034217.19593-38-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:11 -0800 Message-Id: <20180122034217.19593-38-richard.henderson@linaro.org> In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PULL 37/43] target/hppa: Implement LDSID for system mode Precedence: list Cc: peter.maydell@linaro.org, Helge Deller <deller@gmx.de> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	Add hppa-softmmu \| expand [PULL,00/43] Add hppa-softmmu [PULL,01/43] target/hppa: Skeleton support for hppa-softmmu [PULL,02/43] target/hppa: Define the rest of the PSW [PULL,03/43] target/hppa: Disable gateway page emulation for system mode [PULL,04/43] target/hppa: Define hardware exception types [PULL,05/43] target/hppa: Split address size from register size [PULL,06/43] target/hppa: Implement mmu_idx from IA privilege level [PULL,07/43] target/hppa: Implement the system mask instructions [PULL,08/43] target/hppa: Add space registers [PULL,09/43] target/hppa: Add control registers [PULL,10/43] target/hppa: Adjust insn mask for mfctl, w [PULL,11/43] target/hppa: Implement rfi [PULL,12/43] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt [PULL,13/43] target/hppa: Implement unaligned access trap [PULL,14/43] target/hppa: Use space registers in data operations [PULL,15/43] target/hppa: Avoid privilege level decrease during branches [PULL,16/43] target/hppa: Implement IASQ [PULL,17/43] target/hppa: Implement tlb_fill [PULL,18/43] target/hppa: Implement external interrupts [PULL,19/43] target/hppa: Implement the interval timer [PULL,20/43] target/hppa: Log unimplemented instructions [PULL,21/43] target/hppa: Implement ITLBA and ITLBP insns [PULL,22/43] target/hppa: Implement PTLB and PTLBE insns [PULL,23/43] target/hppa: Implement LDWA [PULL,24/43] target/hppa: Implement LPA [PULL,25/43] target/hppa: Implement LCI [PULL,26/43] target/hppa: Implement SYNCDMA insn [PULL,27/43] target/hppa: Implement halt and reset instructions [PULL,28/43] target/hppa: Optimize for flat addressing space [PULL,29/43] target/hppa: Add system registers to gdbstub [PULL,30/43] target/hppa: Add migration for the cpu [PULL,31/43] target/hppa: Implement B,GATE insn [PULL,32/43] target/hppa: Only use EXCP_DTLB_MISS [PULL,33/43] qom: Add MMU_DEBUG_LOAD [PULL,34/43] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] [PULL,35/43] target/hppa: Increase number of temp regs [PULL,36/43] target/hppa: Fix comment [PULL,37/43] target/hppa: Implement LDSID for system mode [PULL,38/43] target/hppa: Implement a pause instruction [PULL,39/43] target/hppa: Implement STWA [PULL,40/43] target/hppa: Enable MTTCG [PULL,41/43] hw/hppa: Implement DINO system board [PULL,42/43] pc-bios: Add hppa-firmware.img and git submodule [PULL,43/43] hw/hppa: Add MAINTAINERS entry

Commit Message

Richard Henderson Jan. 22, 2018, 3:42 a.m. UTC

From: Helge Deller <deller@gmx.de>


Signed-off-by: Helge Deller <deller@gmx.de>

Message-Id: <20180102203145.GA17059@ls3530.fritz.box>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/hppa/translate.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

-- 
2.14.3

diff mbox series

Patch

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 965641f380..76ed7e1ad4 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2200,8 +2200,20 @@  static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn,
     unsigned rt = extract32(insn, 0, 5);
     TCGv_reg dest = dest_gpr(ctx, rt);
 
-    /* Since we don't implement space registers, this returns zero.  */
+#ifdef CONFIG_USER_ONLY
+    /* We don't implement space registers in user mode. */
     tcg_gen_movi_reg(dest, 0);
+#else
+    unsigned rb = extract32(insn, 21, 5);
+    unsigned sp = extract32(insn, 14, 2);
+    TCGv_i64 t0 = tcg_temp_new_i64();
+
+    tcg_gen_mov_i64(t0, space_select(ctx, sp, load_gpr(ctx, rb)));
+    tcg_gen_shri_i64(t0, t0, 32);
+    tcg_gen_trunc_i64_reg(dest, t0);
+
+    tcg_temp_free_i64(t0);
+#endif
     save_gpr(ctx, rt, dest);
 
     cond_free(&ctx->null_cond);