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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:05 -0800 Message-Id: <20180124232625.30105-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 25/45] target/hppa: Implement LCI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.14.3 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 082221f450..41e28ff64c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2462,6 +2462,25 @@ static DisasJumpType trans_lpa(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, DISAS_NEXT); } + +static DisasJumpType trans_lci(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + TCGv_reg ci; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* The Coherence Index is an implementation-defined function of the + physical address. Two addresses with the same CI have a coherent + view of the cache. Our implementation is to return 0 for all, + since the entire address space is coherent. */ + ci = tcg_const_reg(0); + save_gpr(ctx, rt, ci); + tcg_temp_free(ci); + + return DISAS_NEXT; +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_mem_mgmt[] = { @@ -2490,6 +2509,7 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ { 0x04001340u, 0xfc003fc0u, trans_lpa }, + { 0x04001300u, 0xfc003fe0u, trans_lci }, #endif };