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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id r27sm26949344pfj.75.2018.01.28.15.16.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 28 Jan 2018 15:16:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 28 Jan 2018 15:15:23 -0800 Message-Id: <20180128231528.22719-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180128231528.22719-1-richard.henderson@linaro.org> References: <20180128231528.22719-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL v4 38/43] target/hppa: Enable MTTCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 6 ++++++ configure | 1 + 2 files changed, 7 insertions(+) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 70af823a15..7640c81221 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -42,6 +42,12 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif +/* PA-RISC 1.x processors have a strong memory model. */ +/* ??? While we do not yet implement PA-RISC 2.0, those processors have + a weak memory model, but with TLB bits that force ordering on a per-page + basis. It's probably easier to fall back to a strong memory model. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #define CPUArchState struct CPUHPPAState #include "exec/cpu-defs.h" diff --git a/configure b/configure index 96dee6572c..302fdc92ff 100755 --- a/configure +++ b/configure @@ -6555,6 +6555,7 @@ case "$target_name" in cris) ;; hppa) + mttcg="yes" ;; lm32) ;;