From patchwork Fri Feb 9 16:58:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127875 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802240ljc; Fri, 9 Feb 2018 08:58:21 -0800 (PST) X-Google-Smtp-Source: AH8x224LFNEEZYFb2JdD2soJJgcCS6NZdE3n3KAVaSActmEfttBWuF7gUdIIfaHvz+CtcSTFqlcA X-Received: by 10.28.157.139 with SMTP id g133mr2734549wme.114.1518195501502; Fri, 09 Feb 2018 08:58:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195501; cv=none; d=google.com; s=arc-20160816; b=FpQG1qFoTAmJMPfqR8VdTY4P3rJUBhrO++mgllOQH2yLsHbHURv6AA5RD+62Exut6Q aDYqvjx8j9qpxLLP6M+6YJLhXWXQabD8Kvl3yKrr1nrgMRWykzsa3jAPX14ba/qvCaPK eXy/OQF+F3IqxD4lMnsOCIzR0a0RjTXhou3+aesm3bEn34f0+X+tN9Ypmu1yAMFGcIUV zJX62ypj+8cn2Ct1YWa733I/wHzED26tiDaTJl//E+qIsrB2JX0m4s2GiuH7bWtTVTSG EgLSuRSd1KCagZlIDl0pzWCvdeGFNCgrLai1rsjq1RN/2GZrdJBgjOTlsNOGPGCPj3On 3ymQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=iX5+4KX0QoNuJTEmYUrR8SSTKVzn1S4JAWUtVaPRap8=; b=wYYRZHmDZiTRCxgrmMByWHZmuyNRN4mFlSEezAIPU66UeDRFL+yNYPoEOFwW6Hcinz Fz0VkgzlZqWSF43qUecuyb91oIYNEj9K2XCGK8zW1TZ2VUJx2BMK8oD0x0pKp/X56z54 dJJZ5cmBkFDtb+ltOfhXcIhDhGrcJqBKotHn1ep3mmbp2uE3ByOrP9GrCtwFwkrkmK+E blLlfBc5+FsrdRwPauOic85v1kduqkdjhMysp9KUtwRVeLQ7yWwISZsj314HsbUc6//G 7xRMypVijJ2DR/HjlAXIfHyi64dwBAfE9xsLrX4YONUurkr+u4DHK4NMmJUGxDIq16/G W6Dw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 32si2093709wrl.204.2018.02.09.08.58.21 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC0D-000323-1T; Fri, 09 Feb 2018 16:58:21 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 11/11] target/arm: Implement v8M MSPLIM and PSPLIM registers Date: Fri, 9 Feb 2018 16:58:10 +0000 Message-Id: <20180209165810.6668-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> The v8M architecture includes hardware support for enforcing stack pointer limits. We don't implement this behaviour yet, but provide the MSPLIM and PSPLIM stack pointer limit registers as reads-as-written, so that when we do implement the checks in future this won't break guest migration. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ target/arm/machine.c | 21 +++++++++++++++++++++ 3 files changed, 69 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cfa92c477b..3ef523ddbd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -498,6 +498,8 @@ typedef struct CPUARMState { uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ uint32_t csselr[M_REG_NUM_BANKS]; uint32_t scr[M_REG_NUM_BANKS]; + uint32_t msplim[M_REG_NUM_BANKS]; + uint32_t psplim[M_REG_NUM_BANKS]; } v7m; /* Information associated with an exception about to be taken: diff --git a/target/arm/helper.c b/target/arm/helper.c index 7c1dcb0330..03b1a3fd92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10415,6 +10415,16 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return 0; } return env->v7m.other_ss_psp; + case 0x8a: /* MSPLIM_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.msplim[M_REG_NS]; + case 0x8b: /* PSPLIM_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.psplim[M_REG_NS]; case 0x90: /* PRIMASK_NS */ if (!env->v7m.secure) { return 0; @@ -10456,6 +10466,16 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13]; case 9: /* PSP */ return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp; + case 10: /* MSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + return env->v7m.msplim[env->v7m.secure]; + case 11: /* PSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + return env->v7m.psplim[env->v7m.secure]; case 16: /* PRIMASK */ return env->v7m.primask[env->v7m.secure]; case 17: /* BASEPRI */ @@ -10464,6 +10484,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 19: /* FAULTMASK */ return env->v7m.faultmask[env->v7m.secure]; default: + bad_reg: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" " register %d\n", reg); return 0; @@ -10501,6 +10522,18 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } env->v7m.other_ss_psp = val; return; + case 0x8a: /* MSPLIM_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.msplim[M_REG_NS] = val & ~7; + return; + case 0x8b: /* PSPLIM_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.psplim[M_REG_NS] = val & ~7; + return; case 0x90: /* PRIMASK_NS */ if (!env->v7m.secure) { return; @@ -10580,6 +10613,18 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) env->v7m.other_sp = val; } break; + case 10: /* MSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + env->v7m.msplim[env->v7m.secure] = val & ~7; + break; + case 11: /* PSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + env->v7m.psplim[env->v7m.secure] = val & ~7; + break; case 16: /* PRIMASK */ env->v7m.primask[env->v7m.secure] = val & 1; break; @@ -10612,6 +10657,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; break; default: + bad_reg: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" " register %d\n", reg); return; diff --git a/target/arm/machine.c b/target/arm/machine.c index 1a20d6c36c..2e28d086bd 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -246,6 +246,26 @@ static const VMStateDescription vmstate_m_other_sp = { } }; +static bool m_v8m_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8); +} + +static const VMStateDescription vmstate_m_v8m = { + .name = "cpu/m/v8m", + .version_id = 1, + .minimum_version_id = 1, + .needed = m_v8m_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS), + VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 4, @@ -270,6 +290,7 @@ static const VMStateDescription vmstate_m = { &vmstate_m_csselr, &vmstate_m_scr, &vmstate_m_other_sp, + &vmstate_m_v8m, NULL } };