From patchwork Fri Feb 9 16:58:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127869 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802190ljc; Fri, 9 Feb 2018 08:58:18 -0800 (PST) X-Google-Smtp-Source: AH8x225pgFJy1Db6YiMs+ZaxnCklnHYdc9zzf7SMWpqY7rSQnz9MgVeCi+wX5XYElnkEKJ9r5o4x X-Received: by 10.28.108.4 with SMTP id h4mr2413206wmc.161.1518195497939; Fri, 09 Feb 2018 08:58:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195497; cv=none; d=google.com; s=arc-20160816; b=jt1jE+G34X3GGdnO8xBPo9wxJfmlgb+PLd4lMrAlPVdywyzPaNVHZJjrmm6PY+nElx QRvN8nypoZMn276wViH5nA7Q7Ca15NPBEIgIy/j9BYXcPodofscK8YLKQlaquA8HNWRd EHczP6pfl9Ej7u3MtISSNXFyZ0iHzu75CJA2bzD2x3ItD1gek1JnnRFdsjbaQQlXkUTc SX5eAh88f/glH8cjj1HVWaw3veQ5Wgy/cbmLMktNXjqVNjUUB4tqgkgCaarGJhGx8OOF QpPYjfqTgUMRVdSVxg7ZiZNyRsA2KMw8RWUwJLG8V5hPvBUDeSY6xpXkh4oQDfMR5bVs C9rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=ofq501XGiylDEfPk4Zaxl5D/ygK0M/Fl/ptWLJTDpBY=; b=cA53qAfz4zrmcCH0uySQvI9ghiCJjevhzkurr2VJZVPJzPHf75juwEihm4gCvWy5L/ T2Fk/PcnRPeuURQFPjEQfHkGN+kDWpbdp3A8atBcXtWYM9/r6HCQBriPifDNT79NV1VQ uwBEbbzr85M1i0LVaTc2zAn9Q4o5QvqP66aBEUf3dTGf7WtMjGW5j+deFj0e23WjMMO4 HrbqqygnC9gq3mNOj+WUfQepwgwMCAoE8I93X1xLhAjiJqWBIl6L1dZRW7GuHEcpNqkB EV2NaEyRcRFskD4QZgY5EOVo6iuF6wmDuk9jcN7yWcfTR6XYcOuROcKYKVjkE3LQwYMk 9ATg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id n188si1833643wmd.49.2018.02.09.08.58.17 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC09-00030g-Bi; Fri, 09 Feb 2018 16:58:17 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 06/11] hw/intc/armv7m_nvic: Implement SCR Date: Fri, 9 Feb 2018 16:58:05 +0000 Message-Id: <20180209165810.6668-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 +++++++ hw/intc/armv7m_nvic.c | 12 ++++++++---- target/arm/machine.c | 12 ++++++++++++ 3 files changed, 27 insertions(+), 4 deletions(-) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4c1b9e9814..cfa92c477b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -497,6 +497,7 @@ typedef struct CPUARMState { uint32_t aircr; /* only holds r/w state if security extn implemented */ uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ uint32_t csselr[M_REG_NUM_BANKS]; + uint32_t scr[M_REG_NUM_BANKS]; } v7m; /* Information associated with an exception about to be taken: @@ -1258,6 +1259,12 @@ FIELD(V7M_CCR, STKALIGN, 9, 1) FIELD(V7M_CCR, DC, 16, 1) FIELD(V7M_CCR, IC, 17, 1) +/* V7M SCR bits */ +FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) +FIELD(V7M_SCR, SLEEPDEEP, 2, 1) +FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) +FIELD(V7M_SCR, SEVONPEND, 4, 1) + /* V7M AIRCR bits */ FIELD(V7M_AIRCR, VECTRESET, 0, 1) FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 040f3380ec..ea3b7cce14 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -863,8 +863,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } return val; case 0xd10: /* System Control. */ - /* TODO: Implement SLEEPONEXIT. */ - return 0; + return cpu->env.v7m.scr[attrs.secure]; case 0xd14: /* Configuration Control. */ /* The BFHFNMIGN bit is the only non-banked bit; we * keep it in the non-secure copy of the register. @@ -1285,8 +1284,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } break; case 0xd10: /* System Control. */ - /* TODO: Implement control registers. */ - qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n"); + /* We don't implement deep-sleep so these bits are RAZ/WI. + * The other bits in the register are banked. + * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which + * is architecturally permitted. + */ + value &= ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK); + cpu->env.v7m.scr[attrs.secure] = value; break; case 0xd14: /* Configuration Control. */ /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ diff --git a/target/arm/machine.c b/target/arm/machine.c index cae63c2f98..30fb1454a6 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -226,6 +226,16 @@ static const VMStateDescription vmstate_m_csselr = { } }; +static const VMStateDescription vmstate_m_scr = { + .name = "cpu/m/scr", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 4, @@ -248,6 +258,7 @@ static const VMStateDescription vmstate_m = { .subsections = (const VMStateDescription*[]) { &vmstate_m_faultmask_primask, &vmstate_m_csselr, + &vmstate_m_scr, NULL } }; @@ -411,6 +422,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.sau.rnr, ARMCPU), VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), VMSTATE_UINT32(env.sau.ctrl, ARMCPU), + VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } };