From patchwork Tue Feb 20 18:03:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 128951 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp4910216ljc; Tue, 20 Feb 2018 10:03:30 -0800 (PST) X-Google-Smtp-Source: AH8x225uCnxBwLAS1A2KhWB0SIitRgd4AlgEjYdX8GZ9QiURs1UH8qZK1KZFU5V/DovDgpAdXXJB X-Received: by 10.223.160.56 with SMTP id k53mr450557wrk.5.1519149810496; Tue, 20 Feb 2018 10:03:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519149810; cv=none; d=google.com; s=arc-20160816; b=kX9+xpBL7Fv1Gaz9n0m7dNoBpjCCMwo7hw9GS3NsYALFfN+zBfIk6sy1BNSxq29rfM Mp7FdSfGXEJvJ32m9DKSrkQp916+ezeP2IiDN0Yfu+7J6TYFShCaZP9heusWo+RhCD+h PveURQCaHMEqMeJ2zC/O9UY9jSiFikOK+lZzRmYB5wld2IatS9NadT78C+sQ64OeRgPk OeLaSC8j8jvLv0CbAL5mgHR21rQVrBm781Cv8WYeFLwmRjUqs/cX/Nn30OVvHo+hHAyu IZAtRiDYS8dVDW/o5051VsBFCOWzlXQA7NsnJrQ529yPQej1+1urrXhvJVh7A6LS2N+J BNCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=mh7dUpPyL0HYA3nleYLaiCNrahCcX6ec2JmtwubcgdI=; b=ow56AxPQCYg739ByTXMJLUSmLj80WEnqNLn2x8m1V7SOMLQoTNS+wyw3R3FIDsLwhU cTumM0uqpxJ+buIJtyPplRoq3CpkqYPAq9HPjX4EGwUn94CO33RlLP1csXSjuB37YOJg bP+gad3pt/TYipVZFEw473jrmYisRVsfJKswcRDg8gWn3NozgOHvvm6VHyjmaie61qu1 4k5n1/daXY4hf77iL48ZG7b8MtcS+H6y/47Pc+d+Mre2BXAyourtpXvG2G0YvLUJMLbP y9yRB94a/hlGjEPwn+tXl6HphYcRMlaaD6Q6TJ8LZckzyTN3DlR6vte3ka3vFHEma5bJ 98Cg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 59si3040002wrm.374.2018.02.20.10.03.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Feb 2018 10:03:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eoCGI-0008RC-2L; Tue, 20 Feb 2018 18:03:30 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 05/19] armv7m: Forward idau property to CPU object Date: Tue, 20 Feb 2018 18:03:11 +0000 Message-Id: <20180220180325.29818-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180220180325.29818-1-peter.maydell@linaro.org> References: <20180220180325.29818-1-peter.maydell@linaro.org> Create an "idau" property on the armv7m container object which we can forward to the CPU object. Annoyingly, we can't use object_property_add_alias() because the CPU object we want to forward to doesn't exist until the armv7m container is realized. Signed-off-by: Peter Maydell --- include/hw/arm/armv7m.h | 3 +++ hw/arm/armv7m.c | 7 +++++++ 2 files changed, 10 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 35ab757264..5c3f406ccc 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -12,6 +12,7 @@ #include "hw/sysbus.h" #include "hw/intc/armv7m_nvic.h" +#include "target/arm/idau.h" #define TYPE_BITBAND "ARM,bitband-memory" #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) @@ -40,6 +41,7 @@ typedef struct { * + Property "memory": MemoryRegion defining the physical address space * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal * devices will be automatically layered on top of this view.) + * + Property "idau": IDAU interface (forwarded to CPU object) */ typedef struct ARMv7MState { /*< private >*/ @@ -58,6 +60,7 @@ typedef struct ARMv7MState { char *cpu_type; /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ MemoryRegion *board_memory; + Object *idau; } ARMv7MState; #endif diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index facc536b07..189066812c 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -19,6 +19,7 @@ #include "sysemu/qtest.h" #include "qemu/error-report.h" #include "exec/address-spaces.h" +#include "target/arm/idau.h" /* Bitbanded IO. Each word corresponds to a single bit. */ @@ -162,6 +163,11 @@ static void armv7m_realize(DeviceState *dev, Error **errp) object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", &error_abort); + object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); @@ -217,6 +223,7 @@ static Property armv7m_properties[] = { DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), DEFINE_PROP_END_OF_LIST(), };