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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id p9sm4123698pgs.89.2018.02.28.08.48.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 08:48:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 08:48:16 -0800 Message-Id: <20180228164816.24110-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228164816.24110-1-richard.henderson@linaro.org> References: <20180228164816.24110-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [RISU 3/3] Add arm and thumb vqrdml[as]h, vcadd, vcmla X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- arm.risu | 25 +++++++++++++++++++++++++ thumb.risu | 25 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+) -- 2.14.3 diff --git a/arm.risu b/arm.risu index 13ea019..af73345 100644 --- a/arm.risu +++ b/arm.risu @@ -831,3 +831,28 @@ VCVT_rm_neon A1 1111 00111 d 11 size:2 11 vd:4 00 rm:2 op q m 0 vm:4 # Note that sz == 0b11 is UNPREDICTABLE (either UNDEF, NOP or as if == 0b10) # as is cond != 1110 (either UNDEF, NOP, cond-exec or unconditional exec) CRC32 A1 1110 00010 sz:2 0 rn:4 rd:4 00 c 0 0100 rm:4 !constraints { $sz != 3; } + +# +# ARMv8.1 extensions +# +@v8_1_simd + +VQRDMLAH A1 111100110 d:1 size:2 vn:4 vd:4 1011 n:1 q:1 m:1 1 vm:4 +VQRDMLAH_s A1 1111001 q:1 1 d:1 size:2 vn:4 vd:4 1110 n:1 1 m:1 0 vm:4 + +VQRDMLSH A1 111100110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4 +VQRDMLSH_s A1 1111001 q:1 1 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4 + +# +# ARMv8.3 extensions +# +@v8_3_compnum + +# Disable fp16 until qemu supports it. +VCADD A1 1111110 rot:1 1 d:1 0 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } + +VCMLA A1 1111110 rot:2 d:1 1 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } +VCMLA_s A1 11111110 s:1 d:1 rot:2 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } diff --git a/thumb.risu b/thumb.risu index bf7556b..b8afa59 100644 --- a/thumb.risu +++ b/thumb.risu @@ -437,3 +437,28 @@ STR T2 11111 000 0100 rn:4 rt:4 000000 imm:2 rm:4 \ # V8 only instructions CRC32 T1 111 1101 011 0 c rn:4 1111 rd:4 10 sz:2 rm:4 !constraints { $sz != 3; } + +# +# ARMv8.1 extensions +# +@v8_1_simd + +VQRDMLAH T1 111111110 d:1 size:2 vn:4 vd:4 1011 n:1 q:1 m:1 1 vm:4 +VQRDMLAH_s T1 111 q:1 11111 d:1 size:2 vn:4 vd:4 1110 n:1 1 m:1 0 vm:4 + +VQRDMLSH T1 111111110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4 +VQRDMLSH_s T1 111 q:1 11111 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4 + +# +# ARMv8.3 extensions +# +@v8_3_compnum + +# Disable fp16 until qemu supports it. +VCADD T1 1111110 rot:1 1 d:1 0 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } + +VCMLA T1 1111110 rot:2 d:1 1 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } +VCMLA_s T1 11111110 s:1 d:1 rot:2 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; }