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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id g71si612620ywh.133.2018.03.01.03.45.19 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Mar 2018 03:45:20 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55807 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMcJ-0002xt-Ed for patch@linaro.org; Thu, 01 Mar 2018 06:43:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMK3-0003sN-DH for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMK2-0008Cu-Hi for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:27 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46716) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMK2-0008CG-Aq for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:26 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMK1-0000eg-3n for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:25 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:50 +0000 Message-Id: <20180301112403.12487-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org> References: <20180301112403.12487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 29/42] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Neither of these operations alter the floating point status registers so we can do a pure bitwise operation, either squashing any sign bit (ABS) or inverting it (NEG). Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20180227143852.11175-22-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.16.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6f33783a11..9f2c3682dc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11262,6 +11262,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) TCGv_i32 tcg_rmode = NULL; TCGv_ptr tcg_fpstatus = NULL; bool need_rmode = false; + bool need_fpst = true; int rmode; if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { @@ -11380,6 +11381,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) need_rmode = true; rmode = FPROUNDING_ZERO; break; + case 0x2f: /* FABS */ + case 0x6f: /* FNEG */ + need_fpst = false; + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); @@ -11403,7 +11408,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) return; } - if (need_rmode) { + if (need_rmode || need_fpst) { tcg_fpstatus = get_fpstatus_ptr(true); } @@ -11433,6 +11438,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x7b: /* FCVTZU */ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); } @@ -11476,6 +11484,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x59: /* FRINTX */ gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x2f: /* FABS */ + tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); + break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); }