From patchwork Thu Apr 5 17:25:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132877 Delivered-To: patches@linaro.org Received: by 10.46.84.29 with SMTP id i29csp6548797ljb; Thu, 5 Apr 2018 10:25:56 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+0zDuFYJ8bEzJSg+CUJBzkqJXvQZEunAzO8tQ4/vUbn0RFb189ePVP+JCOhO4Cqd4nlbpR X-Received: by 10.28.178.136 with SMTP id b130mr12365023wmf.68.1522949156302; Thu, 05 Apr 2018 10:25:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522949156; cv=none; d=google.com; s=arc-20160816; b=JN3rnXlgecQAuDUtXzqkDBsidh4sDrOGlfnRrUG14rk2ovQBm/NRAO1KAYTB5dUnvU 42lUsjscdSEGVfZybL91kDGCPX/5pZ8/SfC4K3m7skxXywu7DFjiwo4aXw33gCCWGULo yEQDUWOv4qksINuTdVZSIeyDqDh1MtwVKIZlrb/oXk10EhqIf2/dznoNYMVbSD+q6goe 3QcDHy79SSRRFeGL2n5DmeNQ3ER8uXYSZkitOSrKbal99PlI+CscCuGWYn+TI0XL6vPF 5bPqg1/Cdfgw7n6hZTj/4ppF+lRVcYnZ6V9nkbOiP8KP5wCVItlLaBHMO5AsdA4zVTXq coFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:arc-authentication-results; bh=Q4uDNdaJ+4ogrLofV8kJ1HOCMRXLb6ZvGeVI4N+7IWA=; b=x7eLKizoQ7aY6+Q8Ed6+5vEKuRfQ7KnNz9TYZFWHkVYElHHoD/gz85SBkjW4YO0MQ4 0CzOUp4pig5FJqPOkB5pDyvW6/TxE9niaiSo4JZAqUavRN4J4M0ZhJc7Q73h/jWjV5Ax A/67jTNJrPKrFOLUN+d4zjyKhwt9v9j+48EJhAaeqVPPUVGGKayVh2tHvi0Cdyj6LLmY 1dtCM77sXjsokJRH/4gAdLJy+j69Y68c9ZARuAWSDzBJuXtPDudsJvSIksZ6vORLSZg4 4jXeMgZAvTDUQ864lTCZx1JItDe8ubYjVC51FyL9EISLumK1AT2Kql9qblW3C+P6acNr owuA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 94si5963550wrf.176.2018.04.05.10.25.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 05 Apr 2018 10:25:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f48e3-0000o2-1M; Thu, 05 Apr 2018 18:25:55 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Peter Crosthwaite Subject: [PATCH for-2.12] target/arm: Report unsupported MPU region sizes more clearly Date: Thu, 5 Apr 2018 18:25:54 +0100 Message-Id: <20180405172554.27401-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 Currently our PMSAv7 and ARMv7M MPU implementation cannot handle MPU region sizes smaller than our TARGET_PAGE_SIZE. However we report that in a slightly confusing way: DRSR[3]: No support for MPU (sub)region alignment of 9 bits. Minimum is 10 The problem is not the alignment of the region, but its size; tweak the error message to say so: DRSR[3]: No support for MPU (sub)region size of 512 bytes. Minimum is 1024. Signed-off-by: Peter Maydell --- This doesn't really need to go into 2.12, but as a cleanup to a warning message it's pretty harmless. target/arm/helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.16.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/helper.c b/target/arm/helper.c index dcb8476d9e..b14fdab140 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9625,9 +9625,9 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } if (rsize < TARGET_PAGE_BITS) { qemu_log_mask(LOG_UNIMP, - "DRSR[%d]: No support for MPU (sub)region " - "alignment of %" PRIu32 " bits. Minimum is %d\n", - n, rsize, TARGET_PAGE_BITS); + "DRSR[%d]: No support for MPU (sub)region size of" + " %" PRIu32 " bytes. Minimum is %d.\n", + n, (1 << rsize), TARGET_PAGE_SIZE); continue; } if (srdis) {