From patchwork Fri Apr 27 00:26:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 134539 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp89495lji; Thu, 26 Apr 2018 17:29:55 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoiv/0MIEQdNT5upmYR7tqx8Z9FBxsjuuk42GRM+K1Ap0/zBpFBKh+tMbBicOP8MQefRXnv X-Received: by 2002:a0c:d0ce:: with SMTP id b14-v6mr166071qvh.195.1524788995660; Thu, 26 Apr 2018 17:29:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524788995; cv=none; d=google.com; s=arc-20160816; b=whhO+cENnuuAYpGxpD0RtJwz4Muyz6wZM/4ysKgdUGddwvOBxfXk3jyaggMTXxDp/e WVQmk9P0+S1F8lddPeSciecTh+gEtMrYwBvUMeHcZbYxjnkWY2C9oSrroHRUgTRy92Yo kF/iqZHtCT6BAP+ODnTA0RqdOCE/2ZJnASZN0ecoRW4toQxlZAytzbIihL2K+p1GliOI waJxAgQu8jFGmAVi3S/k1ZX7zDzy7m7UH+cVR1yvC2ZXn1xfiwGRVffF8R6MwSUNIoqq oP/XJsRd5vFQN2P3DJbZ/kUBDLwdIgDZWkbthf/FlHbF11EsxSpxaQsyHG8XAfcpOW+8 J9Nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=QeahTyooBey/fkgn97QY2/OE+3ePjf1njf4Fk85eWiw=; b=bcljTHJvJbzra5qEuiU8LidSzXmPyUA1u7jzd/ZatmQ11vKsBZu3GoDvl7kQKwJ/qV RBiMFVsoA+w9twVrsd3vz8wkg+EPqOpVCgbvGZdZocD15W403YL6FIuFEg7JaC0ivk3o S3iUB7NCtennb111AO4cJ04lCgb/Zsmqy2Gyb/lk6VXF2CXuvJoBvZuPIXbihuUftXxi uZxa6fJGZHBoZEsxjkzT4N4WaIr+D7dOdQHOpjujQ6IFnxSKvHZnUGuWZamVEfWSJnQX IXzyW2iazHsqHMPsS5PyrohPrKwA6BDtA16TB1ZyNCLnO6qdBsys7YlRDv99e2NjmJLo SdGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JzZqxuLi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id h6si87073qkj.352.2018.04.26.17.29.55 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 26 Apr 2018 17:29:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JzZqxuLi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45108 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBrGt-0003P9-1v for patch@linaro.org; Thu, 26 Apr 2018 20:29:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51612) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBrE8-0001x4-Iu for qemu-devel@nongnu.org; Thu, 26 Apr 2018 20:27:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBrE7-0004PN-E3 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 20:27:04 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36873) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fBrE7-0004P5-7r for qemu-devel@nongnu.org; Thu, 26 Apr 2018 20:27:03 -0400 Received: by mail-pg0-x242.google.com with SMTP id a13-v6so149203pgu.4 for ; Thu, 26 Apr 2018 17:27:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QeahTyooBey/fkgn97QY2/OE+3ePjf1njf4Fk85eWiw=; b=JzZqxuLi/7pCvfLu0/pxK4n6ij5hONN+PdFuDOKxercO3aCGlNO8neonEuT/cuAs4T N2kT3A7Zyi5QIWgp+sJWRot3d3+dKURCgnDYUOmti3dw38oPnMhgiK8Wc+UutIv46Qv2 hQA3askTbYqJo3+5WyKZycLBsgrq9CmiYtklw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QeahTyooBey/fkgn97QY2/OE+3ePjf1njf4Fk85eWiw=; b=EjLQIN9wmJnUEEAyACVYRPD2FX6wwli55/PYnnJX8+P8V+ZG+1cvOWYo6OOXAQ1HEa kliL3rDCE+FPdpybI0u3Yg269+isNd3r0kFHh8IIEOqcn2E0g6tLNbu5knqZtYO7NKub eoLUKBQtrow5J7cNBaR+5JkfReGCsK4qWWS43SvrOvDMvBpuiDZmBTA8M+n6xb+GjrPn /q3+7UgnDRH1Y3t0SA8Y+taD0qN/GEDswWWZmVfiohA4KTQ+1pCymLUszJKr9hCg8eAH RGWsIctVz5QPSWmYb65Gpc7NIkbwLUw9K/AHklyzghJetye+NZXqvU97hlc3sVqzsSkP ud2A== X-Gm-Message-State: ALQs6tDWXZE4kEZFP3AnCEC17TVpsoffmYDVmfB/vTv8APzBjr7Tf5BV 0SR274v3JeFPjQid44JkzKsamtW1Klc= X-Received: by 2002:a65:438b:: with SMTP id m11-v6mr160802pgp.153.1524788821930; Thu, 26 Apr 2018 17:27:01 -0700 (PDT) Received: from cloudburst.twiddle.net.com ([2605:e000:112b:41da:c94c:5ee7:de92:7d78]) by smtp.gmail.com with ESMTPSA id g76sm86338pfj.102.2018.04.26.17.27.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Apr 2018 17:27:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 14:26:43 -1000 Message-Id: <20180427002651.28356-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180427002651.28356-1-richard.henderson@linaro.org> References: <20180427002651.28356-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 1/9] tcg: Introduce helpers for integer min/max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These operations are re-invented by several targets so far. Several supported hosts have insns for these, so place the expanders out-of-line for a future introduction of tcg opcodes. Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 16 ++++++++++++++++ tcg/tcg-op.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 75bb55aeac..540337e605 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -324,6 +324,10 @@ void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); static inline void tcg_gen_discard_i32(TCGv_i32 arg) { @@ -517,6 +521,10 @@ void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); #if TCG_TARGET_REG_BITS == 64 static inline void tcg_gen_discard_i64(TCGv_i64 arg) @@ -1025,6 +1033,10 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 #define tcg_gen_muls2_tl tcg_gen_muls2_i64 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 +#define tcg_gen_smin_tl tcg_gen_smin_i64 +#define tcg_gen_umin_tl tcg_gen_umin_i64 +#define tcg_gen_smax_tl tcg_gen_smax_i64 +#define tcg_gen_umax_tl tcg_gen_umax_i64 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 @@ -1123,6 +1135,10 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 #define tcg_gen_muls2_tl tcg_gen_muls2_i32 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 +#define tcg_gen_smin_tl tcg_gen_smin_i32 +#define tcg_gen_umin_tl tcg_gen_umin_i32 +#define tcg_gen_smax_tl tcg_gen_smax_i32 +#define tcg_gen_umax_tl tcg_gen_umax_i32 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 34b96d68f3..5b82c3be8d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1033,6 +1033,26 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) } } +void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); +} + +void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); +} + +void tcg_gen_smax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); +} + +void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); +} + /* 64-bit ops */ #if TCG_TARGET_REG_BITS == 32 @@ -2438,6 +2458,26 @@ void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t2); } +void tcg_gen_smin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b); +} + +void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b); +} + +void tcg_gen_smax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a); +} + +void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); +} + /* Size changing operations. */ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg)