diff mbox series

[07/13] target/openrisc: Convert dec_mac

Message ID 20180504054030.24527-8-richard.henderson@linaro.org
State Superseded
Headers show
Series target/openrisc: Convert to decodetree.py | expand

Commit Message

Richard Henderson May 4, 2018, 5:40 a.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/openrisc/translate.c  | 55 ++++++++++++++++++--------------------------
 target/openrisc/insns.decode |  5 ++++
 2 files changed, 27 insertions(+), 33 deletions(-)

-- 
2.14.3

Comments

Stafford Horne May 5, 2018, 5:35 a.m. UTC | #1 
On Thu, May 03, 2018 at 10:40:24PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Acked-by: Stafford Horne <shorne@gmail.com>


> ---

>  target/openrisc/translate.c  | 55 ++++++++++++++++++--------------------------

>  target/openrisc/insns.decode |  5 ++++

>  2 files changed, 27 insertions(+), 33 deletions(-)

> 

> diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
diff mbox series

Patch

diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 90520b0805..8ca01e1a33 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -971,39 +971,32 @@  static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
     return true;
 }
 
-static void dec_mac(DisasContext *dc, uint32_t insn)
+static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn)
 {
-    uint32_t op0;
-    uint32_t ra, rb;
-    op0 = extract32(insn, 0, 4);
-    ra = extract32(insn, 16, 5);
-    rb = extract32(insn, 11, 5);
+    LOG_DIS("l.mac r%d, r%d\n", a->a, a->b);
+    gen_mac(dc, cpu_R[a->a], cpu_R[a->b]);
+    return true;
+}
 
-    switch (op0) {
-    case 0x0001:    /* l.mac */
-        LOG_DIS("l.mac r%d, r%d\n", ra, rb);
-        gen_mac(dc, cpu_R[ra], cpu_R[rb]);
-        break;
+static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+    LOG_DIS("l.msb r%d, r%d\n", a->a, a->b);
+    gen_msb(dc, cpu_R[a->a], cpu_R[a->b]);
+    return true;
+}
 
-    case 0x0002:    /* l.msb */
-        LOG_DIS("l.msb r%d, r%d\n", ra, rb);
-        gen_msb(dc, cpu_R[ra], cpu_R[rb]);
-        break;
+static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+    LOG_DIS("l.mac r%d, r%d\n", a->a, a->b);
+    gen_macu(dc, cpu_R[a->a], cpu_R[a->b]);
+    return true;
+}
 
-    case 0x0003:    /* l.macu */
-        LOG_DIS("l.macu r%d, r%d\n", ra, rb);
-        gen_macu(dc, cpu_R[ra], cpu_R[rb]);
-        break;
-
-    case 0x0004:    /* l.msbu */
-        LOG_DIS("l.msbu r%d, r%d\n", ra, rb);
-        gen_msbu(dc, cpu_R[ra], cpu_R[rb]);
-        break;
-
-    default:
-        gen_illegal_exception(dc);
-        break;
-   }
+static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+    LOG_DIS("l.msb r%d, r%d\n", a->a, a->b);
+    gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]);
+    return true;
 }
 
 static void dec_logic(DisasContext *dc, uint32_t insn)
@@ -1506,10 +1499,6 @@  static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
         dec_compi(dc, insn);
         break;
 
-    case 0x31:
-        dec_mac(dc, insn);
-        break;
-
     case 0x32:
         dec_float(dc, insn);
         break;
diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode
index 20f035f488..7240c6fb77 100644
--- a/target/openrisc/insns.decode
+++ b/target/openrisc/insns.decode
@@ -125,3 +125,8 @@  l_divu          111000 d:5 a:5 b:5   - 11 ---- 1010
 
 l_muld          111000 ----- a:5 b:5 - 11 ---- 0111
 l_muldu         111000 ----- a:5 b:5 - 11 ---- 1100
+
+l_mac           110001 ----- a:5 b:5 ------- 0001
+l_macu          110001 ----- a:5 b:5 ------- 0011
+l_msb           110001 ----- a:5 b:5 ------- 0010
+l_msbu          110001 ----- a:5 b:5 ------- 0100