From patchwork Tue May 15 17:14:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 135905 Delivered-To: patches@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1294428lji; Tue, 15 May 2018 10:14:49 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrPJa82r41Pz8QoM2bWwDMWqsNkWSD5yUdw7Kx4Ao/vBV95AMALb/VGbXlMgq60O9fmA6NF X-Received: by 2002:adf:a4d3:: with SMTP id h19-v6mr10979274wrb.7.1526404489185; Tue, 15 May 2018 10:14:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526404489; cv=none; d=google.com; s=arc-20160816; b=VPXlyLhu8RCLu5TComf3GUAlvf7GJeNb05VxTP+6eE+YNUJK0hFwLY66mja7cf4K2L PwBeyXHWceWc5u2ibV/JlYF7aUeNtL+Z22Wra3mvoHjSKhl7vu8YkcVHoDu1BztXBJOK FL0T9W0Z5U5v0Vplp4XJ1Xv4Cp42aYYsac0OjYQ+xeBOVqVcDzVyPQmjIwRH6S4tmKut NWm/pCJnQUHO5fC1yhDDPw0jssDs6VjJZ06+6/451HqTi+tYcDH8Xj+K8a8eUJaum5QS PFFXVJp8S7m0nKSTJis73Hafby2X8VT74+f1t0mMzrKqpd6Rk0SP9okm+BwTcihoVwH2 8SqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:arc-authentication-results; bh=OGaUEwMyjybu4AXzu4/+uJOMs/d7OgZM52Q3aZflkpU=; b=Jfn5KXbOT03aNj+QTJJ/qMCJgqowjgbAjA7IytLzWtZYzH4gH4w64/lA0jKkEppgbo 4vFjYPP9j1yHKYfMTPjRxPimgb3M9fkyPxRQQtV6AC5IPE50xY25amezxhTmJaLLslIX m9ntzHhqri8kHdvvcri0abExsumo+au1lrZ9/MiYP6nZB5LnRsNPKUgiEG8UBXGHis6b 1vbOSMO29vQVW7OMS8uZYcDsFPW+ppC3nynxxXbu3xa1GYIVW+sYYiMdmk2VmBSgfW7n v5Uk4qn1tB18qE3ZznPe6SC3dg7AgSgTlUfV7i7uxf92+rxddLRH40VxQxgMsBSU0LfA 388A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id o6-v6si423395wri.200.2018.05.15.10.14.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 10:14:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fIdXD-0001cS-Vt; Tue, 15 May 2018 18:14:47 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] hw/arm/mps2-tz: Put ethernet controller behind PPC Date: Tue, 15 May 2018 18:14:46 +0100 Message-Id: <20180515171446.10834-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 The ethernet controller in the AN505 MPC FPGA image is behind the same AHB Peripheral Protection Controller that handles the graphics and GPIOs. (In the documentation this is clear in the block diagram but the ethernet controller was omitted from the table listing devices connected to the PPC.) The ethernet sits behind AHB PPCEXP0 interface 5. We had incorrectly claimed that this was a "gpio4", but there are only 4 GPIOs in this image. Correct the QEMU model to match the hardware. Signed-off-by: Peter Maydell --- A minor nit that I didn't notice when I was modelling this. NB: I think the PSRAM is also supposed to be behind this interface of the PPC, but we definitely can't model that because our PPC implementation won't work for executing code from RAM that sits behind it. hw/arm/mps2-tz.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 8dc8bfd4ab..c5ef95e4cc 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -74,12 +74,13 @@ typedef struct { UnimplementedDeviceState spi[5]; UnimplementedDeviceState i2c[4]; UnimplementedDeviceState i2s_audio; - UnimplementedDeviceState gpio[5]; + UnimplementedDeviceState gpio[4]; UnimplementedDeviceState dma[4]; UnimplementedDeviceState gfx; CMSDKAPBUART uart[5]; SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; + DeviceState *lan9118; } MPS2TZMachineState; #define TYPE_MPS2TZ_MACHINE "mps2tz" @@ -224,6 +225,26 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } +static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, + const char *name, hwaddr size) +{ + SysBusDevice *s; + DeviceState *iotkitdev = DEVICE(&mms->iotkit); + NICInfo *nd = &nd_table[0]; + + /* In hardware this is a LAN9220; the LAN9118 is software compatible + * except that it doesn't support the checksum-offload feature. + */ + qemu_check_nic_model(nd, "lan9118"); + mms->lan9118 = qdev_create(NULL, "lan9118"); + qdev_set_nic_properties(mms->lan9118, nd); + qdev_init_nofail(mms->lan9118); + + s = SYS_BUS_DEVICE(mms->lan9118); + sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); + return sysbus_mmio_get_region(s, 0); +} + static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); @@ -363,7 +384,7 @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, - { "gpio4", make_unimp_dev, &mms->gpio[4], 0x40104000, 0x1000 }, + { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, }, }, { .name = "ahb_ppcexp1", @@ -447,13 +468,6 @@ static void mps2tz_common_init(MachineState *machine) "cfg_sec_resp", 0)); } - /* In hardware this is a LAN9220; the LAN9118 is software compatible - * except that it doesn't support the checksum-offload feature. - * The ethernet controller is not behind a PPC. - */ - lan9118_init(&nd_table[0], 0x42000000, - qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); - create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000);