From patchwork Mon Jun 11 12:56:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 138234 Delivered-To: patches@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4023413lji; Mon, 11 Jun 2018 05:56:37 -0700 (PDT) X-Google-Smtp-Source: ADUXVKK42NXWa1dMyedDc2Koayr9L34ffXrkzmD+O3zgBr165tCYXp23AE6bnffbwvmOcTv796vS X-Received: by 2002:a2e:249:: with SMTP id 70-v6mr9691913ljc.41.1528721797314; Mon, 11 Jun 2018 05:56:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528721797; cv=none; d=google.com; s=arc-20160816; b=CXgo70FahiO3XjjxFTa2kaU7THB28BMAAJgLpVeIVyGjtO+RnzvJjmUs0kvc4F/y8s dAdjrhpwFJPzqbU+4xgmN/VLJaSAAn+t14Rkn0GLvIyxe5nbvxwTQFs839xS7jYiE869 c/r+DKvlU52iUmoqtUpcfQnv6MlyJ2n3TUlVomsLjevbMTfp7QpXVtfIGWYZRMxVVxpK fWwg0vbez/CXlsHFdVOaXdujlIWGSOR94ItRAQ1cY4+lOKQwc06N9vkkZ90xoV54syJp vKjDiwMZCfAA9T4eUYoPJicuK/q8Y3B4IcFoy0sSUOfTHrIihngfQwUOYUQ00d/shfal 1oEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=3PN9ZN6sjgFkxPw3ym4mcbKKBU1Wi3LiJd47SJn6H4E=; b=ruPLd1A0B/qLFJEaj9mPS+Aom68iUuJl/Q7nxHX5/zAi3nfQDRRntRGvz2hs5xv/2L R16fwHut0XsLWfQkOsdvBriDdCB1ldxiv1dCcXVMUzrMos7UVRYcNkzzVSHWGyPpAcQ8 0GPHNoMUfIy4tEfFTSaGSgoFO02hCY9mMPmbjchdMWn1SFaNgT5HZ1zW+oqDE39dOl9u VKdrPAsEu3IOXNKUBvxsGq3Y20u6NslqopvU5KkpG652AnVqsHjt+/ucrrusS0qrChko qybksDpIJlUmnsXsF0Tvx7sxoM0+mSWb59l0wzLYhUGYu996cB8JtoLVV1K6LWNFbE0C ED3A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 78-v6si15524975ljr.367.2018.06.11.05.56.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Jun 2018 05:56:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fSMN9-000743-D3; Mon, 11 Jun 2018 13:56:35 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Paolo Bonzini Subject: [PATCH 1/2] cpu-defs.h: Document CPUIOTLBEntry 'addr' field Date: Mon, 11 Jun 2018 13:56:32 +0100 Message-Id: <20180611125633.32755-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611125633.32755-1-peter.maydell@linaro.org> References: <20180611125633.32755-1-peter.maydell@linaro.org> The 'addr' field in the CPUIOTLBEntry struct has a rather non-obvious use; add a comment documenting it (reverse-engineered from what the code that sets it is doing). Signed-off-by: Peter Maydell --- include/exec/cpu-defs.h | 9 +++++++++ accel/tcg/cputlb.c | 12 ++++++++++++ 2 files changed, 21 insertions(+) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index e43ff8346b1..452e82d21c6 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -127,6 +127,15 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); * structs into one.) */ typedef struct CPUIOTLBEntry { + /* + * @addr contains: + * - in the lower TARGET_PAGE_BITS, a physical section number + * - with the lower TARGET_PAGE_BITS masked off, an offset which + * must be added to the virtual address to obtain: + * + the ramaddr_t of the target RAM (if the physical section + * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) + * + the offset within the target MemoryRegion (otherwise) + */ hwaddr addr; MemTxAttrs attrs; } CPUIOTLBEntry; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 05439039e91..355ded27024 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -664,6 +664,18 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index]; /* refill the tlb */ + /* + * At this point iotlb contains a physical section number in the lower + * TARGET_PAGE_BITS, and either + * + the ramaddr_t of the page base of the target RAM (if NOTDIRTY or ROM) + * + the offset within section->mr of the page base (otherwise) + * We subtract the vaddr (which is page aligned and thus won't + * disturb the low bits) to give an offset which can be added to the + * (non-page-aligned) vaddr of the eventual memory access to get + * the MemoryRegion offset for the access. Note that the vaddr we + * subtract here is that of the page base, and not the same as the + * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). + */ env->iotlb[mmu_idx][index].addr = iotlb - vaddr; env->iotlb[mmu_idx][index].attrs = attrs;